There are voltage regulators designed to have very low noise,
for RF and precision analog applications.
I'm not much of an analog guy, so you probably want to read
through the datasheets yourself :-)
For example, National's LP3999 is an RF regulator with 10uV of noise:
http://www.national.com/mpf/LP/LP3999.html#Overview
Maxim has an app note about reducing noise to 7nV:
http://www.maxim-ic.com/app-notes/index.mvp/id/3656
and finally Wenzel has a number of interesting noise cleanup
circuits:
http://www.wenzel.com/documents/finesse.html
This might be overkill for a 16bit ADC though.
Scott
I'm not much of an analog guy, so you probably want to read
through the datasheets yourself :-)
Also, one should also read Henry Ott's paper, Partitioning and Layout of a Mixed-Signal PCB. He shows that often best way is to keep contiguous ground plane, as any slots will create voltage differences across them. Lowest ground impedance and voltage differentials between different ground points is what you want. At least in EMC tests that has been usually the winning bet
Also, one should also read Henry Ott's paper, Partitioning and Layout of a Mixed-Signal PCB.
http://www.cafelogic.com/articles-2/a-reflow-controller-for-soldering-with-a-griddle-or-toaster/
You have not stated the sampling rate you are using?
If using a high sample rate, you may also wish to ensure the clock used for sampling is also ultra stable. This may require a separate supply just for the clock generator.
The best way to evaluate you noise performance is to capture 2^n samples eg 1024. then perform an FFT on the results.
This will reveal if you have any spurious signals getting in there, degrading performance.
Even better to reveal spurious signals is to average multiple FFT's over time.
Simply seeing one digit of noise is not always indicative of a good sampler.
Have you considered using a separate voltage source for the ADC, a voltage reference chip can supply a small amount of current to a very high precision, +-2mv and under 10ppm temperature drift can be bought off the shelf? You can also use this to reduce the effect of the rest of the circuit on the voltage supply. Are you putting the input signal through any circuitry before it is fed into the ADC?
Thanks. The sampling rate is 10 MSPS.
Let's say the PSRR of an adjustable LDO linear regulator is 50dB. If two such linear regulators are cascaded in series, what will be the effective PSRR? Is it 100dB?
Let's say the PSRR of an adjustable LDO linear regulator is 50dB. If two such linear regulators are cascaded in series, what will be the effective PSRR? Is it 100dB?
That's the magic of db.
Is it possible to parallel two voltage reference chips to supply ADC which requires higher supply current?
Thanks. Is it possible to parallel two voltage reference chips to supply ADC which requires higher supply current?
Thanks. Is it possible to parallel two voltage reference chips to supply ADC which requires higher supply current?
Generally, you would not power the ADC with a reference. Your very expensive (40$?) 16-bit 10MSPS ADC will have a high and low reference pin. If you decide to use an external reference, you would direct the output to the high pin. Take a look at your datasheet, you can not use the power voltage for reference. On that type of ADC it will always be lower. The stability of the reference is more important than the stability of the power rail.
Out of curiosity, what are you using to process these 20Mbytes/sec worth of data?
I wish to design a general purpose control platform with similar concept to dSPACE. We've a dSPACE system in our department. I note that the dSPACE system uses several 16-bit 2MSPS ADCs.
Does that mean you haven't decided what you are going to process the data with? I mean in the short term, right after it comes out of the ADC.
At the moment, I'm thinking of using TI floating-point processor, either C2000 series or C6000 series.