Did you have a chance to take a look at the source code of the updater yet?
No, but I've seen the communication between the pc and the device during the update process and it looked rather straight simple, similar to what thephil described.
I believe the simple "streamer" approach suggested by thephil may be too brittle for this hardware. To build a truly reliable updater, it is necessary to address three critical risks:
1. The "Record Type 05" Trap: The latest firmware (v6.00.2522.079) includes a Type 05 record (Start Linear Address). Legacy STM32 bootloaders often only support Type 00 (Data) and Type 01 (EOF). If the internal parser encounters an unknown Type 05, it may abort the flash. The tool must filter out the :04000005... line, as it is redundant for ARM Cortex-M hardware.
2. Buffer Overflow & Flash Latency: 115,200 baud transmits data faster than an STM32 can erase and write to Flash memory. Without flow control, the UART buffer will overflow, leading to firmware corruption. It is essential to implement a Wait-for-Echo/ACK loop or, at minimum, a 15–20ms inter-line delay to allow the MCU to complete its write cycle.
3. Pre-Flight Checksums: The HEX file should not be trusted blindly. The updater must locally verify all Intel HEX checksums before starting the transfer. If the file on disk is corrupt, the tool should refuse to initiate the flash.
Improving Recovery Logic:Instead of a manual trigger, the implementation should include a "Bricked Device Recovery" button that automatically cycles through baud rates (9600, 57600, 115200) while repeatedly sending the trigger byte until the meter responds. Using a logic analyzer would be valuable to confirm if the meter returns a specific NAK or error code the moment it encounters that Type 05 record.
That is my analysis, of course there may be still room for improvement.