Show us your square wave

[norbert.kiszka]

74LVC14AD from Texas Instruments and modified Rigol DHO924S (removed 250 MHz low pass filter on channels 3 and 4).

Sadly this scope has a sinc interpolation that can't be disabled (until I hack this someday). It goes up to 450 MHz and ~600 ps rise time (800 ps per sample), according to this scope.

[jundar]

74LVC14AD from Texas Instruments...

Does this exact "device" in the first photo generate <nS rise time signal? Could you please share the schematic of it? Thank you.

[norbert.kiszka]

74LVC14AD from Texas Instruments...

Does this exact "device" in the first photo generate <nS rise time signal? Could you please share the schematic of it? Thank you.

If You zoom in first photo, You will probably see that I just shorted 3 (three) pins together - 11, 10 and 9. So one of gates became a ~450 MHz generator connected to input of other gate, output of this second gate (pin 8) is soldered directly into very small BNC female socket - I used "sex adapter" to connect it into scope. Pin 7 is GND and distance between 7 and 8 is good enough to solder both of them into mentioned BNC. Also THT 1uF ceramic capacitor (100 nF is not enough to make that fast rise time). That of course will make something more like sinus than square wave.

After that, I removed this wire (3 pins) and connected external generator (DIY on a separate PCB) ~17 MHz via short as possible wires (both power and signal) into pin 9. Used scope has 1.25 GS/s so there is 800 ps between samples - very likely real rise time was much lower than 800 ps (I guess 600 ps or maybe even faster).

[PartialDischarge]

74LVC14AD from Texas Instruments...

Does this exact "device" in the first photo generate <nS rise time signal? Could you please share the schematic of it? Thank you.

Read this https://www.eevblog.com/forum/testgear/show-us-your-square-wave/msg4510763/#msg4510763

[Folnia]

OK, here's the edges from a very simple pulse generator:

• the source is 5V with no load, but obviously it is used to drive 2.5V into the scopes' 50ohm input
• 4GHz LeCroy HDO4904, connected directly to the scope input with a BNCfemale-BNCfemale adaptor
• 1GHz Agilent MSOS104A, connected via a 1m piece of coax of untested quality

It looks like the 10%-90% risetime is 256ps with a 6.3% overshoot, and the falltime is 453ps with a 3.8% overshoot.

Considering the simplicity of the circuit, that is remarkably fast. It is a simple demonstration that modern jellybean logic (74LVC1G*) generates significant power into the microwave waveband - and hence RF practices are appropriate.

In this circuit a major contributor to the performance is the decoupling capactors, especially the 0V/5V planes and short wide wires, and not forgetting that MLCCs have a very significantly reduced capacitance when there's a DC bias voltage.

My apologies for the quality of the photos; they had to be taken relatively quickly and in non-ideal conditions.

Hi Tggzzz,
I'm not sure about the purpose of having three 74LVC1G in parallel here (it should not be only to get 50ohm resistance).  If one is faster than other two, it seems there might be voltage dividing?
Thanks!

[tggzzz]

OK, here's the edges from a very simple pulse generator:

• the source is 5V with no load, but obviously it is used to drive 2.5V into the scopes' 50ohm input
• 4GHz LeCroy HDO4904, connected directly to the scope input with a BNCfemale-BNCfemale adaptor
• 1GHz Agilent MSOS104A, connected via a 1m piece of coax of untested quality

It looks like the 10%-90% risetime is 256ps with a 6.3% overshoot, and the falltime is 453ps with a 3.8% overshoot.

Considering the simplicity of the circuit, that is remarkably fast. It is a simple demonstration that modern jellybean logic (74LVC1G*) generates significant power into the microwave waveband - and hence RF practices are appropriate.

In this circuit a major contributor to the performance is the decoupling capactors, especially the 0V/5V planes and short wide wires, and not forgetting that MLCCs have a very significantly reduced capacitance when there's a DC bias voltage.

My apologies for the quality of the photos; they had to be taken relatively quickly and in non-ideal conditions.

Hi Tggzzz,
I'm not sure about the purpose of having three 74LVC1G in parallel here (it should not be only to get 50ohm resistance).  If one is faster than other two, it seems there might be voltage dividing?
Thanks!

It reduces the current that each device has to supply. That makes the transition faster, and reduces the consequence of lead inductance.

It reduces the consequence of each output's impedance being a function of the instantaneous output voltage. That makes the overall output impedance closer to 50ohms (i.e. (~7 + 143)/3 is closer to 50 than (~7 + 43).

Differential propagation delay is unlikely to be a noticeable issue with devices from the same batch. A bigger problem is decoupling (di/dt is 2e8A/s) and different wire lengths.

[magic]

Another matter is that FET's aren't exactly linear resistors so their loss increases disproportionately with output current, and absolute maximum ratings are something to consider if you want it to work for long.

[Folnia]

OK, here's the edges from a very simple pulse generator:

• the source is 5V with no load, but obviously it is used to drive 2.5V into the scopes' 50ohm input
• 4GHz LeCroy HDO4904, connected directly to the scope input with a BNCfemale-BNCfemale adaptor
• 1GHz Agilent MSOS104A, connected via a 1m piece of coax of untested quality

It looks like the 10%-90% risetime is 256ps with a 6.3% overshoot, and the falltime is 453ps with a 3.8% overshoot.

Considering the simplicity of the circuit, that is remarkably fast. It is a simple demonstration that modern jellybean logic (74LVC1G*) generates significant power into the microwave waveband - and hence RF practices are appropriate.

In this circuit a major contributor to the performance is the decoupling capactors, especially the 0V/5V planes and short wide wires, and not forgetting that MLCCs have a very significantly reduced capacitance when there's a DC bias voltage.

My apologies for the quality of the photos; they had to be taken relatively quickly and in non-ideal conditions.

Hi Tggzzz,
I'm not sure about the purpose of having three 74LVC1G in parallel here (it should not be only to get 50ohm resistance).  If one is faster than other two, it seems there might be voltage dividing?
Thanks!

It reduces the current that each device has to supply. That makes the transition faster, and reduces the consequence of lead inductance.

It reduces the consequence of each output's impedance being a function of the instantaneous output voltage. That makes the overall output impedance closer to 50ohms (i.e. (~7 + 143)/3 is closer to 50 than (~7 + 43).

Differential propagation delay is unlikely to be a noticeable issue with devices from the same batch. A bigger problem is decoupling (di/dt is 2e8A/s) and different wire lengths.

OK, it make sense, I'd like to build one and test. Thanks

[Gerhard_dk4xp]

74LVC14AD from Texas Instruments...

Does this exact "device" in the first photo generate <nS rise time signal? Could you please share the schematic of it? Thank you.

Probably the same circuit with about the same results:

<    http://www.hoffmann-hochfrequenz.de/downloads/DoubDist.pdf    >

circuit on page 7, scope plots on page 12+.
Sorry for the blue color of the traces.
scope = Agilent 54846B  2.4GHz.

SA = Agilent 89441A

[Folnia]

Hi Tggzzz,
I tested with my board, the rising edge measured is 900ps.  And the bandwidth of the scope is 525MHz.
So the calculation of the the pulse rising edge might be sqrt( 900² - (0.35/525M)² ) , around 604ps, much less than 256ps mentioned in your post. Did I miss something? (I don't find the spec of flip time in the datasheet of SN74LVC1G14DBVR so I guess it's just because of the different component...)

[TurboTom]

From my own experience, the inverters (74LVC1G04 / 74LVC2G04) are better suited for outputting high-speed slopes. The Schmitt-Trigger versions perform well as drivers. You may also consider to interconnect your individual output gates in an "amplified delay line" configuration, i.e. feed the input signal at U6 and take the output at U4 (or vice versa) so the copper delays compensate each other, though the effect at the speeds to be expected here may not be worth the effort.
Moreover, you may try different (quality) brands of the logic chips.

[tggzzz]

Hi Tggzzz,
I tested with my board, the rising edge measured is 900ps.  And the bandwidth of the scope is 525MHz.
So the calculation of the the pulse rising edge might be sqrt( 900² - (0.35/525M)² ) , around 604ps, much less than 256ps mentioned in your post. Did I miss something? (I don't find the spec of flip time in the datasheet of SN74LVC1G14DBVR so I guess it's just because of the different component...)

In your position I would want to understand exactly what the scope is doing. I would play around with whatever settings I could find to try to eliminate that pre-transition "ripple".

Scopes are designed to have good time-domain fidelity, and there are various definitions of such fidelity. That leads to the correspondence with a frequency domain spec (the 525MHz) being complex and potentially misleading. A neat illustration of that is one of my old scopes (Philips PM3410 from 1970), where the front-panel headline performance spec is "200ns risetime", not a frequency.

The "0.35" is a magic number that was derived from non-sampling scopes which have Bessell response input filters. Digitising scopes don't necessarily have that, and some claim that "0.45" is a better number.

[tggzzz]

From my own experience, the inverters (74LVC1G04 / 74LVC2G04) are better suited for outputting high-speed slopes.

Can you expand on that? E.g. how much better and the reason for being better.

[Folnia]

Hi Tggzzz,
I tested with my board, the rising edge measured is 900ps.  And the bandwidth of the scope is 525MHz.
So the calculation of the the pulse rising edge might be sqrt( 900² - (0.35/525M)² ) , around 604ps, much less than 256ps mentioned in your post. Did I miss something? (I don't find the spec of flip time in the datasheet of SN74LVC1G14DBVR so I guess it's just because of the different component...)

In your position I would want to understand exactly what the scope is doing. I would play around with whatever settings I could find to try to eliminate that pre-transition "ripple".

Scopes are designed to have good time-domain fidelity, and there are various definitions of such fidelity. That leads to the correspondence with a frequency domain spec (the 525MHz) being complex and potentially misleading. A neat illustration of that is one of my old scopes (Philips PM3410 from 1970), where the front-panel headline performance spec is "200ns risetime", not a frequency.

The "0.35" is a magic number that was derived from non-sampling scopes which have Bessell response input filters. Digitising scopes don't necessarily have that, and some claim that "0.45" is a better number.

I tried the test on another 2G BW scope. The rising is faster but  there is still ripples before the rising (either before falling edge) . I guess it's because of some front filter integrated in the scope that limits the bandwidth? Do you have any ideas/tests to find out the cause?

And IMHO the major difference between latched inverter and none-lactched one is only the trigger window to avoid multiple flips. And I did a quick test and there seems no obvious changes.

[tggzzz]

Hi Tggzzz,
I tested with my board, the rising edge measured is 900ps.  And the bandwidth of the scope is 525MHz.
So the calculation of the the pulse rising edge might be sqrt( 900² - (0.35/525M)² ) , around 604ps, much less than 256ps mentioned in your post. Did I miss something? (I don't find the spec of flip time in the datasheet of SN74LVC1G14DBVR so I guess it's just because of the different component...)

In your position I would want to understand exactly what the scope is doing. I would play around with whatever settings I could find to try to eliminate that pre-transition "ripple".

Scopes are designed to have good time-domain fidelity, and there are various definitions of such fidelity. That leads to the correspondence with a frequency domain spec (the 525MHz) being complex and potentially misleading. A neat illustration of that is one of my old scopes (Philips PM3410 from 1970), where the front-panel headline performance spec is "200ns risetime", not a frequency.

The "0.35" is a magic number that was derived from non-sampling scopes which have Bessell response input filters. Digitising scopes don't necessarily have that, and some claim that "0.45" is a better number.

I tried the test on another 2G BW scope. The rising is faster but  there is still ripples before the rising (either before falling edge) . I guess it's because of some front filter integrated in the scope that limits the bandwidth? Do you have any ideas/tests to find out the cause?

And IMHO the major difference between latched inverter and none-lactched one is only the trigger window to avoid multiple flips. And I did a quick test and there seems no obvious changes.

I'm not sure what you mean by "latched inverter", but the only thing that should affect the risetime is the output buffers, resistors, decoupling.

I cannot comment on your scope's behaviour. All I can suggest is that you RTFM to see if there are alternative capture modes, e.g. for repetitive waveforms amd non-realtime sampling.

In your traces I cannot see the points where the input waveform is sampled. It is conceivable that the trace you see is a result of software interpolating between points, i.e. a post-sampling reconstruction. In some cases such things can be very misleading. (In general I prefer a scope to present the points on the display, and let my brain do the interpolatation).

I presume you have connected your device directly to the scope input, without a cable.

I presume your scope has a "proper" 50ohm input, not 50ohm//12pF.

[Folnia]

Hi Tggzzz,
I tested with my board, the rising edge measured is 900ps.  And the bandwidth of the scope is 525MHz.
So the calculation of the the pulse rising edge might be sqrt( 900² - (0.35/525M)² ) , around 604ps, much less than 256ps mentioned in your post. Did I miss something? (I don't find the spec of flip time in the datasheet of SN74LVC1G14DBVR so I guess it's just because of the different component...)

In your position I would want to understand exactly what the scope is doing. I would play around with whatever settings I could find to try to eliminate that pre-transition "ripple".

Scopes are designed to have good time-domain fidelity, and there are various definitions of such fidelity. That leads to the correspondence with a frequency domain spec (the 525MHz) being complex and potentially misleading. A neat illustration of that is one of my old scopes (Philips PM3410 from 1970), where the front-panel headline performance spec is "200ns risetime", not a frequency.

The "0.35" is a magic number that was derived from non-sampling scopes which have Bessell response input filters. Digitising scopes don't necessarily have that, and some claim that "0.45" is a better number.

I tried the test on another 2G BW scope. The rising is faster but  there is still ripples before the rising (either before falling edge) . I guess it's because of some front filter integrated in the scope that limits the bandwidth? Do you have any ideas/tests to find out the cause?

And IMHO the major difference between latched inverter and none-lactched one is only the trigger window to avoid multiple flips. And I did a quick test and there seems no obvious changes.

I'm not sure what you mean by "latched inverter", but the only thing that should affect the risetime is the output buffers, resistors, decoupling.

I cannot comment on your scope's behaviour. All I can suggest is that you RTFM to see if there are alternative capture modes, e.g. for repetitive waveforms amd non-realtime sampling.

In your traces I cannot see the points where the input waveform is sampled. It is conceivable that the trace you see is a result of software interpolating between points, i.e. a post-sampling reconstruction. In some cases such things can be very misleading. (In general I prefer a scope to present the points on the display, and let my brain do the interpolatation).

I presume you have connected your device directly to the scope input, without a cable.

I presume your scope has a "proper" 50ohm input, not 50ohm//12pF.

Yes I connected the the board to the scope directly as shown in the attached photo(I also compared with using the 50Ω cable and it shows no difference).
The latched inverter is regarding the suggestion from TurboTom's post " the inverters (74LVC1G04 / 74LVC2G04) are better suited for outputting high-speed slopes. " so I did a quick comparison test.
I'll look into the setting about the capture and 50ohm input of the scope. Many thanks!

[tggzzz]

Those scope inputs will be fine, as is the connection to the scope.

TurboTom didn't reply when I asked him what he meant.

*1G* should be better than *2G* due to the lower lead inductance per gate.

[the Chris]

Leo Bodnar's Fast Risetime Pulser on my new-old LeCroy LC584A with RIS enabled (1GHz, 25GS/s RIS instead of 8GS/s natively).

[rolfdegen]

Rigol MSO5104 (350MHz hack) and Teensy4 CPU as Square generator

My best RiseTime with Teensy4 and parallel GPIO Output is 960ps. Square frequency on Teensy is 100KHz and CPU Clock Rate 600MHz.
I have connected four GPIO outputs in parallel via 51R resistor.





From germany

[tggzzz]

Rigol MSO5104 (350MHz hack) and Teensy4 CPU as Square generator

My best RiseTime with Teensy4 and parallel GPIO Output is 960ps. Square frequency on Teensy is 100KHz and CPU Clock Rate 600MHz.
I have connected four GPIO outputs in parallel via 51R resistor.

Is that 4*(output+51ohm), driving 1Mohm//15pF or 50ohms?

If so, the output impedance would be roughly 15ohms.

[rolfdegen]

New measurement with same circuit and 50R adapter on the scope and 50cm coax cable on the Teensy4 

[rolfdegen]

Rigol MSO5104 (350MHz hack) and Teensy4 CPU as Square generator

My best RiseTime with Teensy4 and parallel GPIO Output is 960ps. Square frequency on Teensy is 100KHz and CPU Clock Rate 600MHz.
I have connected four GPIO outputs in parallel via 51R resistor.

Is that 4*(output+51ohm), driving 1Mohm//15pF or 50ohms?

If so, the output impedance would be roughly 15ohms.

Teensy4 has a programmed output impedance of 23R on each GPIO. The 51R resistors are for current limiting at the output. 50R adapter on the scope and 50cm coax cable on the Teensy4

[tggzzz]

Rigol MSO5104 (350MHz hack) and Teensy4 CPU as Square generator

My best RiseTime with Teensy4 and parallel GPIO Output is 960ps. Square frequency on Teensy is 100KHz and CPU Clock Rate 600MHz.
I have connected four GPIO outputs in parallel via 51R resistor.

Is that 4*(output+51ohm), driving 1Mohm//15pF or 50ohms?

If so, the output impedance would be roughly 15ohms.

Teensy4 has a programmed output impedance of 23R on each GPIO. The 51R resistors are for current limiting at the output.

To get a 50ohm output (to match the 50ohm load) with 4 logic outputs, you would therefore need each resistor to be 180ohms. Then the output impedance would be (180+23)/4 or roughly 50ohms. That would significantly reduce the current drawn from each logic output.

Using multiple logic outputs is beneficial since it reduces the current through each output. It does not, of course, reduce the current through the Vcc and Gnd pins; their inductance will cause the same ground bounce however many logic outputs are used. That's why I like 74LVC1G (rather than 74LVC2G) devices: short leads, one device per package.

The wire between the board and the connector has its own inductance, of course. That can be reduced by reducing its length and/or by multiple wires in parallel and/or replacing it with a flat ribbon.

[rolfdegen]

I'll change my circuit to 4x180R as you suggested and measure again. See you soon.

[BillyO]

If you are going direct into the scope and not using any kind of transmission line (coax) then lowest feasible output impedance is best and drive into a Hi-Z input.  This will help overcome the scope's input capacitance.  Experiment around with the resistor values until you get the best response.  Add some extra decoupling and some bulk capacitance to reduce ground bounce and give the IC it's best chance to drive as hard as it can.  Keep all the leads as short as possible.  Maybe use SMD resistors and re-orient the connector to minimize that ground lead.