"NU180" - A U180 drop-in replacement for the 3458A.

[Kleinstein]

R151 has very little effect. It is really only the last 4 bits and thus quite some tolerance (like 5%) allowed to stay within 1/2 LSB.
The ladder part should no be that critical. If at all it is the part inside U180 that matters with the question of 16.7 K or 16.6 K that would be closer to the theoretical right values.

If there are points to maybe tweak it would be more R154 (604 K: ladder offset) or R143 (reduction of the comparator hysteresis) or R141 (slope amplifier gain, especially in combination with a faster amplifier fur U140).

The extra capacitor in parallel to R140 is also a good point to tweak. A version with doubled diodes for CR140/CR141 also works in a similar direction, reducing the effective diode capacitance and this way speeding things up.
My guess is that the extra speed up is needed because of the extra switch capacitance compared to the original U180.

The turn over test with the external relays for the polarity reversal can work very well. The overall sum should have most of the possible offsets at the amplifier, protection, relay both with a positive and negative sign. So most offsets would cancel out.
With the nasty popcorn noise of a LM399 reference it may help to look at the median and not the simple mean. Depending on the reference one can have a good chance to have some of the cycles without a jump and thus much lower noise.
I use a similar loop for my ADC testing.

The absolute offset in the AZ mode should not be effected very much from the ADC. It is mainly a thing of thermal EMF at the protection, relays and maybe in bias in combination with the relays. The offset is anyway adjusted as a CAL step.
The pull up at the NU180 might have a tiny effect via the ground current, but I don't think the ground current would have much effect.

[KE5FX]

The main source of disturbance in this setup should now be the "long term" noise (below 0.1Hz) of the LM399 and its boost stage. Thermal EMFs should now be calculated out (positive / negative channel) or stay the same for both polarities (connection to reference / short). Same goes for heat related drifts in the 3458A / reference.

Interesting use of the thermocouple scanner, I hadn't seen that done before.  Would it make sense to derive your reference from the 3458A's LTZ1000 rather than the LM399?

[Kleinstein]

The turn over test needs the reference floating to use the switches to get the exact opposite sign. A lower noise reference (e.g. ADR1399 as a simple step up) would make sense. Just a battery may not work as the transient load from swithing may be enough to change the voltage.

If one really wants one could use the same scanner switching (again 4 readings) also for the sum of 2 reference voltages (or the 10 V reference divided in 2 parts).

[Zucca]

Have you guys contacted  Illya of xdevs?

https://xdevs.com/contact/

I bet yes, if not I will be more than happy to do so. He will not post here in the EEVBlog, but for sure he will help.

When he was playing in this forum, his user name was TiN...

He is a legend on the metrology planet!

[Zondar]

I chatted with Ilya a few months ago, prior to this project. I'm pretty sure he'd be interested!

An observation: Adding the pull-downs definitely reduced the reliability of the board. Instead of an error once or twice a day, it's now only a few minutes to a half hour or so. The 114 problems must be addressed more definitively.

[Zucca]

I dropped two lines on the xdevs IRC server...

[DB4UCH]

An observation: Adding the pull-downs definitely reduced the reliability of the board. Instead of an error once or twice a day, it's now only a few minutes to a half hour or so. The 114 problems must be addressed more definitively.

You might want to readjust your series resistor as the skew might have changed slightly with the pulldowns.

What sort of 114 do you get now? (multislope rundown convergence / balanced rundown convergence) (The first one is a timeout in the small slopes (S64 or maybe also S16) while with the second one it’s a failure in the large slopes. (timeout for most likely not reaching a positive state in time))
AFIK if you needed that adjustment to pass the power on self-test, the problem most likely lies with the large slopes as the self-test seems to pass even with the lower slopes missing. Thats the problem with my (now broken) first NU180, it doesn't power on anymore, failing the self-test. Before that it would throw 114 balanced rundown conv. Errors. It now has a lot of glitches in the larger slopes. This variant of the error 114 also appeared on my unit if the capacitor at the slope amp was too large. (here it was also failing in the larger slopes)

My second NU180 has been running stable ever since, it hasn't yet thrown a 114 in normal operation. My very first board threw one once or twice a day or so. (with the modified lower slope resistors, after moving the components to a new PCB and removing the modification, I didn't get any on this board either AFIK (for both cases (with pulldowns installed and without them) before killing it, of course )

Greetings,
Simon

P.S. I can now be found in the xDevs IRC as well. (I had lurked there before but never really participated much)

[Zondar]

It produces "multislope rundown convergence" errors.

My current board has already suffered some minor damage due to repeated changes of resistors, and I can't risk much more of that unless I'm quite sure that it will work. I could increase the R140 capacitance again, maybe to 20 pf, and see if that helps, but Simon's experience with increasing it wasn't very encouraging.

Any other ideas? I'm working towards being able to control and read out the instrument via GPIB, but that's not going to be very useful if the machine won't run reliably.

Maybe it's nearing time to think about an updated design? Add pull-downs on all control lines, or maybe move to a different CPLD/FPGA? What else? On my latest board, I included nesting pads so that different sized resistors (e.g., different levels of cost or precision) can be used - that's very handy while experimenting.

A question about monitoring CAL72: If looking at long term drift, does it matter if ACAL's are performed along the way? I don't think so, but I want to be sure.

Edit: After adding pull-downs, the CAL72 drift has been running net 0.11 ppm/day so far. However, it's not really that good, as intermediate measurements have been in the range of +/-0.5 ppm/day due to short term noise in the measurements.

[Kleinstein]

The drift of the CAL72 value would not be that critical. The SN18 limit of 0.43 ppm/day is not so much because this would be a problem, but to indicate a bad U180 that will likely drift more.
There is a chance the drift will settle somewhat after 1 or 2 weeks of usage. This would be humidity and stress effects after soldering the FR4 PCB.

Additional noise for ACAL could indeed be an issue. For the normal measurements one has the option to integrate a bit longer, but for ACAL the times for the measurement are fixed.

For the additional tweaks there is a chance that a little capacitance (1-2 pF range) between one of the switch control signals and the integrator (e.g. sum2 / sum3) could help with the error 114. The integrator seems to have too much positive output voltage and thus negative input charge at the end of the fast (S256) rundown. One could add some positive charge with a capacitor from the control signal (for a positive ref. path) that turns on when S256 ends. This would effectively modify the switch charge injection.
The other point would be reducing the capacitance (e.g. 200 pF to 150 pF) at the integrator (on the A3 board) and this way get less delay at the integrator.
More capacitance at R140 is likely the best bet.

I don't see the CPLD as the weak point. It is more the switches with additional capacitance, maybe a little more delay (here the FF part in the CPLD would also contribute) or the charge injection of the switches as likely source for the tendency for error 114. Parasitic capacitance could contribute to charge injection in the "wrong direction". So the point to maybe try would be different switches, not so much a different CPLD.

[DB4UCH]

It produces "multislope rundown convergence" errors.
I could increase the R140 capacitance again, maybe to 20 pf, and see if that helps, but Simon's experience with increasing it wasn't very encouraging.

The point at which the larger slopes started to fail was between 30 - 40pF, so you could try increasing it to 20pF, for such loading it still worked in my case. If your board is already somewhat damaged it would leave it be for now.
To see if the underlying issue is the same as on my board, you could try to probe the slope amp out (TP140), the integrator (TP112) while triggering on the control signal for S64 and then look for differences between failed and working conversions. (use the Triggered mode on your scope, so it only updates the waveform on a new trigger event, this should give you the failed state if one were to occur) [But the scope probe at TP112 can already stabilize it slightly, i.e. you might not be able to do this measurement with the capacitor installed]

In my case I noticed that, for failed conversions, the S64 slope at the slope amp out had a different slope than for a working conversion. (~1.5V / 800ns vs. ~2V / 800ns) But at the same time the slope at the integrator itself didn't really change for failed vs working conversions. The exact reason why this sometimes was the case, I don't know, but speeding up the slope amp helped here.

About CAL72: This value gets updated by the ACAL DCV. So, to properly track it one needs to run an ACAL, and then get the temperature (for TC correction) and CAL 72 constant and repeat that for a few times over a few days, ideally over GPIB.

For an updated design, I'm currently modifying MiDis first design slightly. (adding pulldowns and gate modulation) The reason for adding the gate modulation is that @wanghar has it on his boards and those show noticeably lower noise than my boards. Although it can be disabled as well if the need were to arise.
I attached the schematic below, I'm currently still working on the PCB, I will put it on GitHub once I'm finished.

Greetings,
Simon

[Zondar]

I think it would be good if one design could be shared by participants. That may mean a little accommodation or negotiation, but it could pay off.

The other boards like MiDi's are probably better-designed than mine since I constrained it in size and shape, which resulted in compromises.

Obviously, pull-down resistor positions on all control signals are needed if the current CPLD is still used (it seems OK with pull-downs).

Including gate modulation is fine if it can be disabled.

I'd include more decoupling in places.

A discussion about grounds is timely. Some such as AGND1 and AGND2 can be combined, which should lower the impedance to A3's ground and reduce layout hassles as a bonus. (I've thus-far kept all of them separate.)

MiDi used 4 resistors for the 50k. That doesn't work for me at the moment, and I'm not convinced that there's a benefit from that (there certainly could be). He suspected that such arrays led to problematic levels of higher capacitance, though. Is your plan to continue using 4 at a time?

Since I invested in some custom foil resistors, I really need 2512 footprints for the 80k's and the single 50k, 1206's for the 37.5 resistors, and 805's for all other U180 resistors. The larger than 805 footprints are necessary for foil resistors above 25k. What I did on my last board was include redundant footprints for the few that are larger than 805's so that, for example, 2512 vs. 805's could be chosen after the fact. The two footprints were nested together, one inside the other. All other components probably shouldn't be smaller than 603's or else manual soldering becomes very difficult.

What other changes are worth considering?

Edit: I increased the R140 capacitance to 20 pF, and that has clearly helped. It's only been a short while, but no 114's so far.

[DB4UCH]

A discussion about grounds is timely. Some such as AGND1 and AGND2 can be combined, which should lower the impedance to A3's ground and reduce layout hassles as a bonus. (I've thus-far kept all of them separate.)

I would keep them separate (for now), as it seems like that’s the way it's done on the original U180. And maybe an as low as possible impedance here isn’t really what we want as there is an inductor on the original A3 board before connecting to GND.

MiDi used 4 resistors for the 50k. That doesn't work for me at the moment, and I'm not convinced that there's a benefit from that (there certainly could be). He suspected that such arrays led to problematic levels of higher capacitance, though. Is your plan to continue using 4 at a time?

The biggest benefit I see is that here the influence from self-heating of the input resistor is reduced. This could otherwise lead to an INL error, especially with highish TC parts (10PPM/K for example)

Since I invested in some custom foil resistors, I really need 2512 footprints for the 80k's and the single 50k, 1206's for the 37.5 resistors, and 805's for all other U180 resistors. The larger than 805 footprints are necessary for foil resistors above 25k. What I did on my last board was include redundant footprints for the few that are larger than 805's so that, for example, 2512 vs. 805's could be chosen after the fact. The two footprints were nested together, one inside the other. All other components probably shouldn't be smaller than 603's or else manual soldering becomes very difficult.

I think that just changing the footprints (while keeping the position about the same) shouldn't create big differences. So, we should be able to have boards that are slightly different while not changing too much of the general behavior.
The only issue I see is with the ladder, as it needs to be pretty tight (physically) to not have too many parasitics. As its only really responsible for the last few bits, we don't really need better TC resistors. Of course we can also put a different footprint here. (Although I'm not too sure if it makes sense, even with custom resistors)

Greetings,
Simon

[Zondar]

Well, I still think a common design would be a benefit to all, but there are still many different things worth trying, so maybe it's too early for that. If my current board holds up as reliable enough to run over GPIB, and it's looking very good so far, then I'll be satisfied with it for a while anyway.

A few points:

It's no-doubt true that the specs on some resistors are not as important. If someone wanted only the critical 80k's and 50k, for example, the cost would be about $125 plus shipping and any taxes/tariffs. I haven't seen any 80k's better than 0.1% and 10ppm in the wild, so it could be worth it.

I haven't calculated this, but I'd guess the current density in a 2512 resistor will be roughly 1/3 that of an 805, and any heating would be spread over something like 6-9x the area. So one 2512 should be at least as good as a set of four 805's. (To be clear, 2512 is the smallest of this type that can reach 80k.)

I do encourage you to join the ground pins that are obviously connected together on A3. That includes the two that go through a single inductor. But I was paranoid about this myself, so I understand the reticence.

It's not clear yet, but I don't think CAL72 is "drifting" in a constant direction like my genuine U180 was. So far it looks more like just moving around a little with temperature or just from noise. I don't have climate controls on where it's located, so there's easily a 10 C or more change over a day. I guess if I did 10 ACALs close in a row I could see about how much variation due to noise shows up.

Adding deliberate charge injection to the switches may be a good idea in theory, but it would probably be too delicate to accomplish in practice.

[Kleinstein]

If the extra capacitor at R140 is sufficient, I would also avoid tweaking with an extra capacitor from the control. The capacitor at R140 should help with both the error 114 and the maybe timeout for the S1 slope that may not contribute.

With the really good 50 K resistor one should get away with only 1 resistor. Spreading over multily resistors is a thing with smaller lower grade ones.

With the rather low R_on ADG734 or similar there should be little need for the gate voltage/ supply modulation. The error goes down with about the square of R_on. With the ADG734 I would prefer the same supply.

Supply modulation would be a thing for lower capacitance and higher resistance switches like 74LV4053, but that would be a different version. It would be interesting in combination with 100 K resistor arrays and a +-15 V reference.

[Zondar]

Increasing the R140 capacitance to 20 pF has allowed my current board to run without error. I haven't noticed any bad side effects yet.

Unfortunately, the GPIB adapter I bought will not do. What hardware (i.e., controller) and software are people using, or would suggest?

[voltsandjolts]

Which adapter do you have and what are its symptoms of not working?

There is this;
https://www.eevblog.com/forum/projects/poe-ethernet-gpib-adapter-open-source-project-now-public/

[aronake]

Increasing the R140 capacitance to 20 pF has allowed my current board to run without error. I haven't noticed any bad side effects yet.

Unfortunately, the GPIB adapter I bought will not do. What hardware (i.e., controller) and software are people using, or would suggest?

E5810A or E5810B rocks! Lan to GPIB. It seems to be the gold standard. Then python + PyVisa or python-vxi11. BTW thanks for absolutely awesome work on this!

[DB4UCH]

I've now mostly finished the PCB layout for the second PCB revision. I've kept the footprints the same as they were previously. If one needs specific footprints i.e. single 80k / 50k, I think an individual modification of layout to accompany this shouldn't change the behavior too much. Therefore, I think it's fine if we have slightly different versions in this regard. The gate modulation can also just be disabled.

https://github.com/simonbauch/3458A_U180_replacement_PoC/tree/REV_A

If you see any sort of problem / have any sort of criticism, write it here. I have kept the grounds (agnd1 and agnd2) separate because I didn't really find a way to nicely combine them in the layout and I didn't want to change too much yet.

Greetings,
Simon

[Zondar]

E5810A or E5810B rocks! Lan to GPIB. It seems to be the gold standard. Then python + PyVisa or python-vxi11. BTW thanks for absolutely awesome work on this!

Those are obsolete but available used, typically for around $400.

The one by Kofen looks like a good candidate.

What about all those "genuine" (actually counterfeit, I presume) National Instruments or Agilent GPIB to USB adapters?

[Zondar]

So I made a board using TMUX1134's instead of ADG734's to try to see if there are any advantageous performance differences in practice. They look like they should be fully interchangeable, but it doesn't work, leading to an immediate hardware failure. Although I've seen this before and have recovered via various tweaks, it feels like this is a more fundamental problem.

I haven't studied it in great detail yet, but if anyone wants to play Sherlock Holmes, compare both and see if you can figure out why. It's probably something basic that I missed and am still missing. 

[wanghar]

@Simon, when designing the new PCB, it is recommended to add a JTAG high-voltage (12V) unlocking circuit. Doing this just connect a 2K resistor in series with pin 38 of the ATF1502 and reserve a 12V input port. I'm not sure what tool you use to program the ATF1502x chips, but when I use OpenOCD for programming, I heavily rely on this unlocking step first. If the JTAG is locked and unable to download the program, apply 12V voltage to this port (the current is very low, <1mA), then program the 1502_erase.svf file first. After successful programming, remove the 12V voltage and proceed to program the NU180 svf file. This method has a 100% success rate.

I also conducted tests with pull-down resistors. By adding 5K pull-down resistors to each of the four 80K control signals, the gain error issue in the negative voltage range was significantly improved. Using another 3458 for comparative testing, the INL caused by gain error within the 0 to -10V range has been reduced to 0.4ppm, compared to the previous 5–6ppm. The INL within the 0V to +10V range remains below 0.1ppm. This is a huge progress, thanks for your investigation!

Regarding resistor selection, it is indeed challenging to decide due to factors such as size, accuracy, and temperature coefficient. However, for now, it is reasonable to recommend using one LT5400 to replace the two 10K resistors for the +12Vref to -12Vref conversion. I think this part can be finalized first.

[Kleinstein]

The TMUX1134 has a different pinout - so it would need a different PCB.   Electrical it looks rather similar, but there could still be a slightly higher delay and this is what can cause the error 114 and start up issues.

For a new layout it can be a good idea to have the clock line to the CPLD kind of shielded to reduce capacitive coupling to the control signals to the switches. The control lines change the impedance with the state and this would effect the capacitive loading to the clock line. Even with the canned oscillators there is still a small effect of the load capacitance on the frequency and this would cause an INL error. Transients from switching could come on top. A ground trace inbetween should reduce the capacitive coupling quite a bit.

[Zondar]

The TMUX1134 has a different pinout

But it does have the same pinout. What differences do you see?

[Kleinstein]

The TMUX1134 has a different pinout

But it does have the same pinout. What differences do you see?

Indeed the pinout looks the same. It is the 1st page drawing of the ADG734 that is different.
So sorry for adding confusion.

[tridac]

Have you thought about using the next higher value from 80k, then using a higher value shunt resistor to fine tune down to 80k ?.