"NU180" - A U180 drop-in replacement for the 3458A.

[Kleinstein]

With the ADG734 at least R_on get more dependent on the signal voltage when the supply voltage is lower. Even though R_on is still low with 3.3 V supply, the derivative to the signal voltage gets large and this would suggest that R_on is no longer linear anymode.
dR_on/d_Us looks like 5-10x higher at 3.3 V compared to 5 V supply.
With less than 4 V supply the supply voltage modulation may be needed to avoid the U² INL part from the nonlinear R_on.
So one should than at least plan with the option to use the modulation.

One may get around this with addition negative supply (e.g. -1 V and +3.3 V).

[Zondar]

With the ADG734 at least R_on get more dependent on the signal voltage when the supply voltage is lower.

The question is what do you believe is bad about powering the switches at 5V while using say 3.3V control signals?

I just don't see a reason why that's a concern. The device is designed for this, and I've measured R_on using as low as 2.5V control signals on a 5V supply, with no noticeable change in performance.

Also: It appears that Lattice wants users to buy rather expensive licenses to use their software. Is that true? What would people propose to use instead? Edit: Apparently, you can "request" a free license for at least some versions. Even if so, this is an annoying nuisance that I'd normally walk away from given that other vendor's software is genuinely free.

[iMo]

Do ask Lattice whether you may get the LSC-SW-ISPLEVER sw free (usually 1y license). It is an older sw (2020, up to win7) so perhaps you may get it free for hobby use (they do it with IceCbe2 and Radiant)..

[Zondar]

Do ask Lattice whether you may get the LSC-SW-ISPLEVER sw free (usually 1y license). It is an older sw (2020, up to win7) so perhaps you may get it free for hobby use (they do it with IceCbe2 and Radiant)..

Sure, because it's so awesome to have to beg permission for a normally $700, time-limited, license that you can't rely on having access to in the future. Also, windows only. 

Edit: Right, the last supported version is windows 7! This is a "yeah, no!" for me.

[iMo]

..so all roads lead to XC9536.. 
PS: Perhaps the "ISE14.7 for Win10/11 virtual machine install" includes all the licenses already.. The vanilla ISE14.7 is for win7, with some hacking it works under win10 too (and needs a license file)..
You will need a programmer - the xilinx_clones (DLC9LP) from ali/ebay (around $33) work fine usually..

[Zondar]

..so all roads lead to XC9536.. 
PS: Perhaps the "ISE14.7 for Win10/11 virtual machine install" includes all the licenses already.. The vanilla ISE14.7 is for win7, with some hacking it works under win10 too (and needs a license file)..
You will need a programmer - the xilinx_clones from ali/ebay (around $33) work fine usually..

With a quick look, the Lattice one is not clearly better or worse than the Xilinx one for our purposes. It's a legacy product, but is still officially current, though their obsolete support and licensing issues are contentious for me.

I downloaded the Linux version (good on Xilinx for supporting that). I haven't installed it yet, but I don't believe any licensing is required. You do have to fill out a form, but there doesn't seem to be any other gate-keeping. I may still have an old official Xilinx programmer around somewhere too, though I haven't seen it in a decade or more.

I'd prefer to hear of support or objections (can't find the parts, etc.) amongst the active participants before going for a new CPLD. I think Kleinstein may still have some concerns about voltage levels, for example.

[Zondar]

Hello Barry,

That's an interesting project you have there! Welcome!

[Barry Ward]

Hello All,

I need a U180 !   I was delighted to find this thread and maybe have something to add. 
(disclaimer, I'm a complete idiot, with tenacity) I did not have time to read all of the posts (yet) but have an ongoing project and a tiny bit of knowledge that might be useful.   

I am making a laser trimmer (IR laser, 0.03mm spot) I've successfully trimmed some metal chip resistors manually and am currently adding the CNC part.

It seems like the next step for this project might be to evaporate some test alloys on a stable base (quartz?), trim them and test for tempco with the idea of making our own resistor hybrid.    I already have a few magnetron sputter coaters for my SEM and could modify for thermal evaporation if that's what it takes...   

I'm wondering if the tempco might be trimmable maybe by juggling the trim geometry against the substrate material properties.

regards

Barry
Merritt Island, FL

PM me for a local geekout
(reposted due to image rotation)

[Barry Ward]

I did not find any SMT resistor trimmers other than big commercial machines.  I've trimmed them with a diamond file and tested for long term stability which seems to be amazing despite all of the internet urban legend that says it will never work.   

It's 2025 so resurrecting an ancient technology with some modern components seemed appropriate.   ESP32, Diode laser, 3D printed parts, old XYZ stage.

(I'm old, we were laser trimming hybrids in the 70's...)   Seems like the resnet inside of the U180 is laser trimmed...

[Kleinstein]

For the voltage levels the issue is the possible additional current when a 3.3 V logic level is used with 5 V supply. The DS is not very specific about this. It should be relatively easy to measure how the supply current behaves depending on the voltage to an logic input.
The problem is not the extra supply current (should still be relatively low like 0.1-1 mA range) but the point that the supply current would be modulated with the signal. The matching between the channels may not be good enough (especially not when 1 chip  is doing the positive ref. and another the negative references).

A point that could still be tested with the old HW may be changing to the other clock edge. From the description is may have a chance to work and would be a lot easier when external FF are used.

Trimming the TC may be possible, but it first need a measurement of the TCs of the partial resistors.
Evaporating the alloys may be tricky, as the components have a different vapor pressure. So the film composition can differ from the source material. It may be easier with sputtering. Fine trim of the TC can be done by annealing with some alloys.
Producing good resistors (e.g. <20 ppm/K)  is a big task and for U180 one would want very good ones.
I don't consider making your own resistors feasible for an U180 replacement.

[KE5FX]

I don't consider making your own resistors feasible for an U180 replacement.

Not at commercial scale, of course.  But for one-offs where the performance over time and temperature can be checked, why not?

[Zondar]

For the voltage levels the issue is the possible additional current when a 3.3 V logic level is used with 5 V supply.

OK, we discussed this earlier a time or two.

My assumption is that, if anything is going to upset the supply, it will be the CPLD in general, and its outputs specifically, rather than the switch's internal control signal buffer. For example, every pin with a 5k pull-down is consuming ~1 mA when high, and that's obviously modulated as switches are turned on and off. This is another reason why we should move away from pull-downs. 

Per my tests, I'm confident that using 3.3V control signals with a 5V supply will not affect the switch's analog performance. I can't recall if I measured the switch's power consumption under that specific condition, but I never saw it use more than a few tens of nA. It's a bit of a pain, but I can test it again to allieviate any further concerns.

I did think a little about trying the rising edge. It's close, but if it worked, it would be better than inverting the clock, and of course there would be no need for a new CPLD. Unfortunately, my "golden" board won't accept new programming, and I don't want to mess with my current board either.

Edit: Installing the ancient ISE software failed with my Arch-based linux version due to unresolvable dependencies. I will hold my nose long enough to try it on W10.

[iMo]

..if I were you I would run the ise14.7 VM version - the 15GB image you download (not the vanilla install) - in oracle virtualbox under your Arch linux..
When under win10 run it also in virtualbox - that is the easiest option..

[Zondar]

I successfully installed it on Linux now.

After installation, it does require a license, though a free one should be available. I haven't dealt with that yet.

[Zondar]

OK, I looked at power consumption vs. control signal voltage level.

Conditions: Vdd=5V for all measurements, Vcc=0V, either DC or 100 kHz, with all four channels used.

At DC (actually 0.1 Hz), my 6.5 digit DVM has a very hard time measuring the power consumption, but maybe it's around 3 nA. It was too difficult to detect changes vs. control voltage. During transitions, I did observe the expected spikes, peaking a little over 100 nA at 5V, and dropping as the control voltage is reduced. They appeared to be mostly capacitive in nature, e.g. the magnitude inverted depending on the direction.

I also ran it at 100 kHz, with all channels used and clocked simultaneously. Here is control voltage vs. power consumption:

5.0V: 30 uA.
4.5V: 28 uA.
4.0V: 24 uA.
3.5V: 17 uA.
3.3V: 15 uA.
3.0V: 10.5 uA.
2.5V: 5.8 uA.
2.0V: 1.9 uA.
1.5V: 0.033 uA.
1V: essentially 0 uA.

[Barry Ward]

Hello All,

I've had time to read all of the posts.  I have zero experience with the 3458 (except for troubleshooting mine to the U180).
I've used the ATF CPLDs.   I have the following summary observations based on what I've read.

 - Take a careful look a the clock voltage and transition times. It propagates through everything.  Rise times might be an issue or solution.

-  re: the resistors and drift.   Don't discount mechanical strain.   Try this to see:   Mount an smt resistor (any type, metal, carbon, whatever) on a thin piece of G10 (superglue) I used the edge breakoff parts from PCBs to demo this. (like 0.2" X 10") , Attach some thin wire.   Measure the resistance.  Bend the board.   If your results are like mine, you will never be able to unsee that effect.  Soldering, mechanical strain and relative orientation (on dividers esp) are a thing.  You are building a strain gauge.  Physics is a thing.

-  consider making the resistor network a seperate board.   I (and/or others) can (more) easily do some tempco testing and balance tweaking. (plus laser trim them..)

and, Thank you all for all of your work and perseverance.

Barry

hand trimmed metal glazed 1206 to 400 ohms

[Zondar]

-  consider making the resistor network a seperate board. 

I've been thinking about that for a while, mostly so I could swap a more expensive set of resistors amongst different boards. The main issue is how to connect two boards with low capacitance and without growing the assembly much taller. Hirose, for example, has some good low-profile connectors, but I have only a mm or so left unless I dispense with the inner-most shield.

[Barry Ward]

Zondar,


Here's what I'm thinking:

Stage 1
* Make a PCB with edge contacts or maybe use some tiny connectors,  I have an assortment of the 1.27 mm dual row headers so that might be the way I go if I have to work on my own fork of the layout. (I'd rather cooperate)
  - Try to make the board in a way that the "hybrid" could replace the resistor board If the thing actually works.
  - That way if I fail or die you can just continue.   A separate resistor board seems like the way to go for thermal isolation and some type of conformal coating anyway.
  - Of course I'll video and record what I do so it can be recreated by others.   Whatever I do I'll likely try to make it a process so I can make batches of them to be had by others should I succeed.

Stage 1.1
* Order or hornswaggle a board or 2 and get my meter going.

Stage 2:
-  Try sputter coating a microscope slide with whatever alloys I can find.    Shoot for some nominal resistance per square in the middle of the network values.
-  I have ceramic but no saw at the moment.   Maybe we can find some hybrid blanks of a suitable size..but one or more alternate substrates need to be waiting.
-  Start with Manganin (CuMnNi) because I can cut that from a shunt.  No clue if it will work.  NiFe Alloys might work too.
-  Figure out the contact method and materials.   Consider that any connections have a tempco too...(likely very small but..)
-  Laser trim to a specific value. Test for stability and Tempco.  I have a small chamber that will go to -60C and to too hot so some good stress cycles can be had.
- - If that can be made to work, coat and etch the network pattern, laser trim and test.
- repeat until the end....

Stage 2  (minus 0.00000001)
-  Stick down some stable chip resistors and trim them.  (just make a hybrid)

Other "Mundane Details"  https://youtu.be/3fGHaVn5rGo

Do you or others have a good photo of the resnet?  I've only seen a partial photo from Extrasolar.   A nice scale square hires photo would be helpful.
You might want to consider using the same resistor network pinout (order) for connection to your board - if you make an external resistor board.

best regards,

Barry

[Kleinstein]

OK, I looked at power consumption vs. control signal voltage level.

Conditions: Vdd=5V for all measurements, Vcc=0V, either DC or 100 kHz, with all four channels used.

At DC (actually 0.1 Hz), my 6.5 digit DVM has a very hard time measuring the power consumption, but maybe it's around 3 nA. It was too difficult to detect changes vs. control voltage.

This is a good result - so the ADG734 (and similar) are OK with a  3 V control and 5 V supply.
The pull downs are indeed some issue and not ideal - a reason to get them relatively large if possible. On the good side, during run_up there are allways half the channels active and half the channels inactive. So the sum should be constant. The same point should also apply to the switch supply currents.

I am a bit skeptical about separate resistor and switch boards - the extra connector adds resistance and capacitance. This may be OK for an initial test, but would not be a good permanent solution.

There a photos of the resistor network. However there is really no need to reproduce it exactly. Not all resistors need to match, some are in separate pairs and not all are equally critical. The main critical  part are the 4 x 80 K and 1 x 50 K, with than to a lower degree 4 x 20 K. E.g. the 2 x 10 K pair for the 12 V  to -12 V is perfectly fine with a separate set of equal resistors (e.g. LT5400, div23 ?). With separate switches the mayout can also be quite a bit different.
So far the main difficulty is with the CPLD and switches, not so much the resistors. If needed one may still consider tweaking some of the resistors (e.g. the 7 V to 12 V step) to adjust the gain TC, if really needed. Long term dirft is taken care of by ACAL and is thus not that critical with the 3458 than with some other DMMs (e.g. the 3456).

[bnz]

...
Do you or others have a good photo of the resnet? ...

Someone needs to send a defective U180 to Noopy and we will have nice pictures 

[MiDi]

...
Do you or others have a good photo of the resnet? ...

Someone needs to send a defective U180 to Noopy and we will have nice pictures 

U180 die shots on xDevs: https://xdevs.com/guide/life_with_3458/#u180

[Barry Ward]

Kleinstein,

I just happen to have a resistor hammer, so I can hit it. 

I have not seen much on the temperature testing front but in addition to functional testing there are potential stability issues.
I'm just now learning the system and its nuances.    I suspect that everything adds up to having the edgy failures and starting with all the metrics as close to perfect as possible will help.

I've made hard things before and just maybe there is something I can contribute.

Have you built a board or are you just another outside observer like me?

[Barry Ward]

MiDi,

Thank you !!

Very helpful  (no resnet photos but the graphic and the photos of other modules explains a lot, plus the tolerance goals information from the HP journal)

I now have a different direction as to the resnet.    It should directly attach to the U180 pins with only the 8 connections to the CPLD switch board being separate.

It seems possible to make a board (or ceramic hybrid) using precision metal resistors with a similar layout so everything that might couple will at least be in the same direction as the original part.
Then it can also be laser trimmed to exact values required.    If there is a tempco the resistors can be trimmed to the correct side of the warmup or aging curves.

If I get a chance tonight I'll fire up Kicad and see what will fit in that space.

best regards,

Barry

[Zondar]

Since I bought some expensive foil resistors, it would be nice for them to be portable, e.g. via a "hybrid" board. However, this is difficult to do without introducing compromises such as increased capacitance, so I haven't planed to actually do this. Barry: you should go for it.

I'm still struggling to make a decision about the CPLD issue. The easiest path in some ways is to stay with the current one and add external latches. We already have at least 4 designs using the ATF's at present, so maintaining continuity with that should be helpful to some, plus they are still manufactured and supported. On the other hand, adding external latches is less efficient and it may add a bit of noise. We won't know without trying.

For latches, the TI one I pointed out earlier has split supplies, so it can run at 5V in and 2.5V out, even, which the switches do appear to handle well. Or else just 5V latches (e.g. 74xx374's) should do, with no need for voltage regulation. Of course, they are triggered on the rising clock edge, which has to be dealt with.

It would be great if someone could try out the rising edge, which should be a simple modification of the current CPLD code. (I'm not in a very good position to do this myself right now.)

[DB4UCH]

Yesterday I played around with the noise a bit and now I am asking myself how much of this noise actually originates just from the S4 / S1 step. Those steps definitively don't have timeouts so if those slopes aren't able to finish in time you just lose resolution. (I.e. your LSB gets a lot larger)

Now for my experimentation, I found out that a slight trim of the reference voltage (with the C at the slope amp) was able to slightly reduce the noise. (up to a certain point as when you increase the 5V reference too much you start to fully lose the smaller slopes leading to heavily increased noise.) The same was observable by doubling the capacitance at the slope amp, but this led to issues with the larger slopes failing with a cold unit, so this isn't a proper solution. I also had lower noise with my very first NU180 where I increased the 16.5k to 16.62k.

The reason why I think that the lower slopes might be the primary noise sources is that, at 1 NPLC, the resolution is specified to be 25 Bits so with +-12V of range this results in an LSB of 0.715µV (might be smaller on a real unit, but the point still stands). The RMS noise for a good U180 lies in the 600nV range, so ~1.6µV Vpp, so jumping by one or two LSBs around zero. This noise might therefore originate to some part in a misdetection of the S1 slope.
But if we were to also have such trigger / misdetection issues with the S4 slope we will naturally also get more noise, how much more exactly depends on how often this were to happen.

Here I postulate that properly selecting the resistance ladder values / 5V reference voltage R604 etc. we might be able to reduce the noise noticeably. (I think wangar has done some trimming on his ladder resistors and he has quite good noise performance so this might be some part of the reason for his better noise.

What do the others think about this thesis?
(Another thing: shielding doesn't seem to influence noise much if the 5V reference is not trimmed, if you have a trimmer pot sticking out from the NU180 PCB the aluminum shield has noticeable effect on the noise)

Anyway, Hello Barry! Nice to have you here!

@Zondar about the CPLD issue: I don't really know either. 

If one of the CUPL experts here is willing to tell me how to invert the clock and what exactly I should measure I should be able to do that before Christmas.

Greetings,
Simon