Author Topic: Paid Gig] High-Speed PCB Layout for Sipeed Tang Nano 20K Carrier Board (DAC904,  (Read 6557 times)

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Offline christos chrisTopic starter

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Hi everyone,

I am looking for an experienced hardware engineer to design a custom PCB layout on a paid basis (freelance / contract).

The project is a carrier board based on the Sipeed Tang Nano 20K (Gowin FPGA) and needs to integrate the following parts:

- Sipeed Tang Nano 20K module interface
- DAC904 (14-bit, 165MSPS High-Speed DAC)
- 7" HDMI Display interface (HDMI connector / TMDS differential pairs)
- Power Management Section (Multi-rail voltage inputs, DC-DC buck regulators / LDOs for the required FPGA and DAC voltage rails)
- User IOs (Push buttons / tactile switches and status LEDs)

Since this is an FPGA-based design, precise pin mapping is not yet locked in the schematic. The designer can perform pin-swapping / pin assignments to optimize the layout and routing.

Requirements:
- High-speed digital routing with strict length-matching between the FPGA IOs and the DAC904 data bus.
- Differential pair routing for the HDMI lines with 100 Ohm differential impedance control.
- Proper power integrity (PDN) design, multi-rail power distribution, and isolation between digital and analog planes (especially for the DAC904).
- Multilayer PCB design (4 or 6+ layers) with dedicated power and ground planes.
- Deliverables: Full project source files (preferably KiCad or Altium).

If you have experience with FPGA board design, high-speed converters, and power management layout, please send me a PM (Personal Message) with a link to your portfolio, examples of previous work, and your estimated rates.

Thank you!
 
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Online langwadt

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half of that seems to make little sense. the tang nano 20K is module that already has a hdmi connector and all the supplies needed, DAC904 is very old, and strict length-matching for 165MHz?
 
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Offline christos chrisTopic starter

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Thanks for the feedback!

To clarify, I am a hobbyist working on a custom project, and I might have over-specified a few things in the description.

1) You are right about the Tang Nano 20K onboard HDMI. I am mostly focused on creating a clean carrier board to route the DAC904 and the power stages/buttons properly.
2) I chose the DAC904 because it fits my current design requirements and it's what I have available to work with.
3) Good point on the 165MHz. It might not need extreme sub-millimeter length matching, but since I am not an expert in high-speed layout, I prefer to hire someone who can guarantee a clean, noise-free design.

If anyone is interested in helping me out with this layout on a paid basis, please send me a PM!
 

Offline AndyC_772

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Hi, professional engineer here, though I'm afraid I'm too busy to take on this job otherwise it's the sort of thing I might offer to do.

DAC904 is listed by Mouser as EoL and scheduled to be discontinued - but regardless, you really don't need length matching, just a well specified setup and hold relationship between the clock and each of the data signals in the FPGA. Who's writing the .SDC file?

 
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Offline pcprogrammer

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I'm a hobbyist and not an expert, but I have experience.

The Tang Nano 20K might not be the best fit for this project. Why, because a lot of the IO pins on the board are already used for the on board peripherals and might not allow for the 165MHz connection to the DAC904.

I have played with it and found that basically only 7 IO pins are completely free to make use of. The rest are either used for the 40 pin LCD connector, the HDMI connector, the audio amplifier, the LED's, etc.

A better fit would be the Tang primer 20K module, but this does need HDMI interfacing on the carrier board to be made. I also found it to be cheaper than the Tang Nano 20K. But if you already have a Tang Nano 20K, you can always strip the board a bit to get rid of the unneeded stuff. https://www.eevblog.com/forum/fpga/cheap-fpga-development-board-brs100-gw1nr9/msg6184685/#msg6184685

You can save yourself some money, by doing the job yourself. It is not that difficult and EasyEDA pro has support for length matching and differential pair routing. JLCPCB is very cheap when the board is kept below or equal to 100mm x 100mm. Even 4 layer is not that expensive, especially when you don't mind to wait a couple of weeks for your board. Select the cheapest shipping option and it will only cost about 12 euros including the new EU import duty.

Also a good learning experience.  :)

I have designed a 4 layer board that has gigabit ehternet and a T113-S4 MCU in EasyEDA pro with length matching and differential pair routing and it was not hard at all. Sure took a little bit of reading the help file and practice a bit, but the board worked on the first try. (Except for one stupid mistake: https://www.eevblog.com/forum/projects/i-can-use-a-second-set-of-eyes-on-my-t113-s4-design/msg6284978/#msg6284978)

When you are worried about EMI and compliance, it becomes a different story. The Tang Nano 20K might be very bad in this respect, and no carrier board can fix that.

Offline christos chrisTopic starter

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Good morning, the purpose of doing this is to make a DDS 0-30MHz  needs a 7' screen HDMI The DAC 904 Or if someone else suggested, You will need it. PCM 1808 For audio input, inputs for control and on-screen display of Watts, ref, swr, volts, amps, temp, And whatever else you need. I'm also thinking about four buttons, for selecting menus and settings. I write the files, if you can take it on, we can discuss the price.
 

Offline christos chrisTopic starter

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Good morning my friend, there is no need to remove the components above the board!! Unless they have no contact with the central pads, I haven't looked yet if they have no communication I don't know if I'll make it yet 😀
 

Offline pcprogrammer

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Good morning, the purpose of doing this is to make a DDS 0-30MHz  needs a 7' screen HDMI The DAC 904 Or if someone else suggested, You will need it. PCM 1808 For audio input, inputs for control and on-screen display of Watts, ref, swr, volts, amps, temp, And whatever else you need. I'm also thinking about four buttons, for selecting menus and settings. I write the files, if you can take it on, we can discuss the price.

Why the HDMI for the 7 inch screen, while there are cheap RGB 7 inch screens that are easy to use. For instance this one: https://www.aliexpress.com/item/1005005292813240.html

I would also like to suggest using for instance a F1C100s MCU in collaboration with the FPGA to make it easier and allow for a cheaper FPGA to be used. The MCU can be used to drive the LCD and read the buttons or a rotary encoder, while the FPGA makes up the DDS. Adding a touch panel can eliminate the need for buttons.

I never really finished it, but I worked on something similar. See https://www.eevblog.com/forum/fpga/why-does-this-dds-code-fail/msg4066636/#msg4066636
There is more information in my repository here: https://github.com/pecostm32/Lichee_Nano

Is this a commercial enterprise or just a one of for you to play with?

Offline christos chrisTopic starter

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With a quick glance, the 40 pins on the screen without removing it can easily be used for DAC 904, I choose hdmi To gain pins, logic and speed, if you can take it on, let me know in a message.
 

Offline pcprogrammer

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With a quick glance, the 40 pins on the screen without removing it can easily be used for DAC 904, I choose hdmi To gain pins, logic and speed, if you can take it on, let me know in a message.

Yeah for reducing pins, HDMI makes some sense.

But sorry, not a job for me. Got plenty of my own ideas to keep me busy.

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Hello, I have enough experience for this, and if this is going to be the final product, I can design an EMC-focused system for you. I've sent a DM.
 
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Offline 1997circuits

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Interested — this is the kind of board I do.

Background: US-based circuit design engineer, 30 years. Day job is hardware
at a tech company; my own practice takes commercial and medical work.
Recent example: a 12-layer, 6,100-pin RFSoC board (Gen3 RF data converter,
DDR, 10GbE).

A few things I'd want to get right here, so you can judge whether I'm the
right person:

1. The parallel bus is the real constraint, not the DAC. At 165 MSPS the
setup/hold window on the 14 data lines plus clock is tight enough that length
matching and reference-plane continuity matter more than anything else on the
board. I'd keep the whole bus on one layer over unbroken ground, with a return
via at any layer change.

2. Jitter shows up as SFDR. Clock path routing and where the clock source sits
relative to the DAC will set your spurious-free dynamic range at high output
frequencies more than the analog output stage will.

3. Split AVDD/DVDD, but a single ground plane. The 904's output switching dumps
noise back into the digital supply. Local decoupling on separate rails — but I
would not split the ground plane; that usually creates worse return-path
problems than it solves.

4. One question that could simplify the whole layout: are the FPGA pin
assignments fixed, or can they be re-mapped? On the Gowin part the bus pins are
reassignable, and re-ordering them to match the DAC pinout can remove most of
the crossovers — often one fewer layer and a noticeably cleaner board. If the
RTL is already written it's a small change on your side and a large one on mine.

To quote it I'd need the schematic (Altium preferred, but KiCad/OrCAD/PDF are
fine), board outline and mechanical constraints, target layer count if you have
one, connector and mounting requirements, and whether you want fab/assembly
files or just the layout database.

How I work: fixed price quoted up front with the assumptions written out, so
you can see what's driving the number. No hourly meter. Payment split across
milestones, and progress you can look at rather than silence until delivery.
US-based entity to contract with; happy to sign an NDA before you send anything.

Reply here and I'll follow up — I can have a fixed price and schedule back to
you within a day.
« Last Edit: July 30, 2026, 04:58:42 pm by 1997circuits »
 

Offline SamElectronics616

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Hi,

I’m interested in your FPGA carrier board PCB layout project. I have experience with high-speed PCB design, FPGA-based hardware, multilayer board layouts, differential-pair routing, power distribution, and signal-integrity considerations.

I can support the Tang Nano 20K carrier board design, including:


DAC904 high-speed interface and controlled-length data-bus routing
HDMI TMDS differential-pair routing with 100 Ω differential impedance
FPGA pin assignment and pin-swapping to optimize routing
Multi-rail power architecture, DC-DC converters, and LDO placement/routing
Analog/digital power and ground partitioning around the DAC
Controlled-impedance stackup and high-speed signal routing
Length matching and timing constraints for the FPGA-to-DAC interface
4/6+ layer PCB layout with dedicated ground and power planes
Design-rule and manufacturing checks

I can provide the complete editable PCB project files in KiCad or Altium, along with the manufacturing-ready Gerber and drill files.

Please send me the schematic, component datasheets, preferred PCB layer count/stackup, and any mechanical constraints you have. I can review the requirements and provide an estimated timeline and fixed/project rate.

I’d also be happy to share relevant examples of my previous high-speed FPGA and PCB design work.

Best,
Sam
 


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