Via stitching not showing filled holes in 3D

[aiq25]

Hello. I'm trying to stitch two traces sing 1.5mm via's with 1.1mm drill size. I created a pad for this but in 3D drawing it's showing the pads as holes that are not filled. Am I doing something wrong?

Attached are some screenshots of the pad setting and the 3D rendering. I just want to make sure the via's are filled.

[whalphen]

Check to see if the holes get included in the Plate-Thru Holes drill file.  If so, and if you have copper on both sides of the board at each hole, I think you'll be OK. The 3D rendering doesn't control what gets plated thru.  The drill files do.  The holes in the PTH drill file get drilled early in the process -- before the plate thru step.  The holes in the Non-PTH drill file get drilled after the plating step.  Besides being in the PTH drill file, there has to be copper on both sides of the board at the hole location for the plating process to work.  If you're expecting the holes to be filled with metal, I don't think that's normally done.  Check with the PCB manufacturer to see if they can fill the holes with metal.

[SiliconWizard]

The 3D viewer doesn't "tent" vias, so what you see is perfectly normal (at least it works as intended). Stitching vias are just vias. Nothing special.

Now if you are expecting to see not tented (meaning covered by solder mask), but rather filled vias, I don't think that's supported by the 3D viewer, and not sure this is supported by KiCad in general either (AFAIK you can only set a via as blind, buried or through-hole at this point). If anyone knows how to explicitely set a via as filled in KiCad, please let me know.

And as whalphen said, not all PCB manufacturers can actually do that, and when they do, that can be a pretty expensive option. I'd suggest doing that only if you have a very good reason to, and then you'd have to instruct the manufacturer explicitely as it won't show in KiCad's output files (again AFAIK, if anyone knows how to, don't hesitate to mention it).

[bpiphany]

As pointed out, vias commonly aren't filled (or plugged). They are often small enough for the soldermask to cover them though.

If you do not render the board or soldermask in the 3D-viewer you actually get a pretty good picture of where there is copper and not.

[aiq25]

Thank you for the replies. I thought they would be filled but it makes sense now.

We used plated through filled via's at work and I just realized those are set separately and are called out in our drawings. The via's in this design doesn't need to be filled, I'm mostly experimenting.