If you make the vias larger and leave them untented you can always let the wave solder process fill them with solder making a nice low resistance path, or if you are hand soldering the boards, manually fill the untented vias up with solder afterwards.

that doesn't do anything ... it is still the circumference of the plated wall multiplied by the thickness of the copper on the plane it is connecting to that defines the resistance... you have that bottleneck where you leave the plane and where you connect the plane.

if your outer layer copper is 30 micron and the hole is 1mm then the connecting stub from hole wall to trace is diameter * pi wide , and 30 micron tall. that is the cross section the current has to weasel through.

so if you have a trace that needs to be 1mm wide at 30 micron thick copper for current carrying capability then the hole in the via cannot be smaller than 1/pi.

for a 0.3 mm diameter drill you will end up with a circumference of 0.3 times pi = 1mm which is equal to your track width.

so if you need a 75 mil trace and you plonk in a via that is smaller than 75 / pi ( 25 mils ) you have a resistance discontinuity.

now, the discontinuity in the wall itself comes form the fact that the copper there is only half that. so that hole diameter should be at least (2/pi) times the trace width to maintain cross section.

current capability of a wire is given be cross section.

a wire that is 2 mil thick and 5 mils wide can carry the same current as one that is 1 mil thick and 10 mil wide. it is length * width.

hopping from a trace to a via you have the cross section given by copper thickness * via circumference

in the via itself the equation is still (copper thickness * via circumference) but in the via itself copper is only 1/2 size thick

and exiting the via on the other layer you are again faced with copper thickness * via circumference.

so you need to calculate for worst case :

2 x trace width ( the two is to compensate for the half thickness in the holes ) / PI to get the drill diameter.

Now, this is ONLY valid if your plated thickness is 1/2 that of your outer layer copper !

the real formula is more complicated.

(trace width * trace height) = (cirumference of hole * trace height) for the trace to via handoff

(trace width * trace height) = (cirumference of the hole * thickness of the via plating itself ).

you will find that the latter equation is the one that is dominant ( unless you get into whacky aspect ratios with very small currents)

filling via' only solves the latter equation. if the circumference is still too small you will fry the trace to via handoff interconnects at the demand current.