Analog frontends for DMMs approaching 8.5 digits - Discussions

[Kleinstein]

One would normally need C504 or C524 too for the compensation, not just C525. One can argue to have C504 at the same or twice the value of C525.

[julian1]

Maintaining a ratio between the capacitors for op-amp output to inverting input, and the non-inverting input to gnd, has a logic to it. 
Using 33p/68p it is stable at DC.
Although not stable enough to probe jfet Vos with a multimeter without oscillating. I can increase the cap values, but might wait to see if it's more stable when configured with more gain.

I have swapped scope probes, calibrated them, and reorganized so all measurement is done at the DUT.
Bode plots look about the same, without or without the inductor. I think it's not in the GBW region for the inductor to matter much.
Output tendency at higher freq is to slew like an integrator.

[Kleinstein]

The closed loop performance is not very sensitive to compensation and amplifier details. That is the point of a an amplifier with feedback. At the high frequency end (e.g. > 500 kHz) the inductor is expected to have little effect. The inductor adds additional gain and reduces the noise (reduce the noise of the source resistors) for the low frequency part. Without the inductor the source resistors would be the major noise source for the amplifier.

It would be more in a high gain case that one should see the effect of the inductor. For a test of the amplifer it could make sense to do a test with very high gain (e.g. 1000 or 10000 if the DC offset allows). The higher frequency end is then close to the open loop response and this can help to check / understand the compensation part.

The TL071 is known to be a bit sensitive to capacitive loading. So one may have to use a series resistor at the output for things like a DMM. This could be an issue already with the gain switching CMOS mux. The times 1 case may need a little series resistance before the mux.

[iMo]

Mind your inductor has some self-resonance (due to its parasitic capacitance)..

[julian1]

Mind your inductor has some self-resonance (due to its parasitic capacitance)..

The frequency of inductor self-resonance, will be max impedance, and thus reduced amplifier gain. I think it will be above 500kHz-1MHz where it doesn't matter though.
But it would be interesting to confirm for a specific inductor choice for reference.
One thing I saw when investigating looking at Bode/DSA plots, is the capability/hack for impedance plots by using an injection transformer, in a with a sense-resistor to measure both voltage and current. 
It's something to try, at some point.

[julian1]

With amplifier configured for 1000x non-inverting gain (47.5k/47.5R), and input tied to gnd, output reads -1.420V.
This should correspond to a 1.4mV jfet Vos


After adding a second op-amp U505 (with 1000x gain), on independent supplies (for controllable CM offset and cmrr test), the main amplifier oscillates.

The second op is too slow (with high-gain) to be included as part of the feedback loop.
Adding 100p at C508, as a fast bypass, doesn't seem to help.
I can try a faster op-amp with better GBW (tried opa202, then mc33172 ).
Edit. second op has no local gain, so it may help to increase its compensation (C513).

Alternatively I am not certain the second op-amp actually needs to be part of the feedback loop of the main amplifier for a CMRR test.
Instead, it should be possible to just use the second amplifier to amplify the main-amplifier (configured as buffer) to a useful value to be sampled with a DMM.

[Kleinstein]

The test with high gain would be to see the JFET offset, maybe look at the noise/drift and to get an idea of the open loop response of the amplifier to judge the compensation. So this test should be done with only a single OP-amp.

The idea of using the compound amplifier configuration with a 2nd OP-amp in the loop is to get more speed for the cases with high gain, especially a gain of 100.
This way the gain of 1 no longer needs to be 100 x faster than the gain of 100.
The 2 amplifiers can than share the gain in a way that the 2nd amplifier is still well faster (e.g. 2 x the BW).
With a realistic speed (e.g. 10 MHz GBW) the 2nd OP-amp would not take all the gain, but only a part, like half the gain, maybe a little more.
For a gain of 1 the 2nd amplifier would also have a gain of 1.
For a gain of 10 the 2nd amplifier should also have a gain of about 5. So the BW in x10 mode could still be 50% of the x1 case.
For a gain of 100 the 2nd amplifier should also have a gain of about 10-20. So the BW in x100 mode could be 10-20% of the x1 case.
This should still be fast enough to get resonable fast settling even with the gain of 100.

The 2nd OP-amp is optional (the 3458 does not have it). Especially for the start a somewhat slower response at gain 100 is OK.
I don't think the final use with a high resolution ADC would need a gain of 1000. In that case the 2nd OP amp would however make sense as a BW of only some 2 kHz wpuld be a bit on the low side.

The CMRR test would normally be done with a gain of 1. So no need for the 2nd OP-amp.

[julian1]

Ok, that makes a lot of sense. I wasn't sure why a compound op might be preferred versus just dropping in a faster op.
Equalizing the bandwidth to be more independent of gain is definitely a nice property - even without adding extra gain ranges.
But it re-raises the question of resistor part choices.
And gnd current compensation with two resistor dividers is more complicated - ie. 34420a.
Rather than one divider there are two, so we have to sum their currents (by summing output voltages) I think.

[Kleinstein]

The GND current compensation is not that bad: the first OP-amp has essentially no current to ground. Both gain divider chains are driven from the output side, so just the higher current. Even if there are multiple independent dividers to ground it is easy to add the contributions at the inverter for the compensation. It is just another resistor.

The 2 step FB divider in the 34420 is for different purposes. The main point is likely the internal calibration check / calibration of the highest gain. There are different ways to get the medium high gain settings and this allow a calibration of the 1 mV range from 100 mV ref source. So no need for a special calibration sources.
The other point could be getting a little less noise from the FB divider. The 2 stages allow for a little lower resistance and thus noise in the FB path. I still don't hink that is the main part here. It can be an issue for even lower noise.
In my oppinion a compound amplifier would have made some sense for the 34420, because of the quite large gain. The high gain is slow, but the noise anyway makes very fast measurements less attractive. The source resistor switching provides some adaption in the GBW, but no extra DC gain.

The frequency compensation at the FB dividers itself gets a bit tricky though. It gets tricky if the 2nd stage has a not so flat frequency response. So there should be suitable capacitors to compensate for the capacitance of the switches. It does not need to be as good as for a scope or AC measurement, but still reasonable (e.g. +-30%) accurate. So the choice of the mux chip for the gain could effect the small capacitors.

For the parts choice the 2nd OP-amp should be resonable fast, but it does not need to have the input CM range all the way to the positive side. In my DMM front end I have an TLE2071 (had it at hand). I would also consider a OPA1677 or OPA197 or about any reasonable low power, 32 V capable OP-amp with some 8-20 MHz GBW. A reasonable good slew rate can also help.
The more tricky choice is the 1st OP-amp, as one wants it to work well (many rail to rail OP-amps fail just in the relevent range or 0.5-3 V from the rail) near the positive supply. So the reasonable choices are TL071, TL071H, TLE2071 and similar. I don't consider the GBW that critical, it is more about having no too much complications in the phase response up to some 3 MHz.
I consider the current speed fast enough - the point of not going much slower is avoiding a larger inductance.

[julian1]

I think it makes sense to properly characterise and test the one op-amp amplifier in priority.
With that said, the extra op-amp (meant for cmrr) is provocatively almost  in a compound configuration (DP adg1209 could work in SP adg1208 footprint).

The frequency compensation at the FB dividers itself gets a bit tricky though. It gets tricky if the 2nd stage has a not so flat frequency response. So there should be suitable capacitors to compensate for the capacitance of the switches. It does not need to be as good as for a scope or AC measurement, but still reasonable (e.g. +-30%) accurate. So the choice of the mux chip for the gain could effect the small capacitors.

For reference, how are you choosing or calculating values for switch compensation values?
   
I see the following,
      10p across 60k         
      22p across 100k.   
      39p across 4.7k   

Perhaps independent resistor dividers for each ratio instead of a ladder, would make it easier.
That way each divider could get a dedicated value capacitor.

[Kleinstein]

I totally agree to first sort out the 1 OP-amp version. The 2 OP amp version is mainly to speed up the x 100 case somewhat and make the front end part work more like the x 10 case. So it still needs the 1 OP-amp version to work properly. The compensation at the FB divider should be about the same even with the 2nd OP amp added for more speed. The 2nd OP amp is more like making the compensation of the JFET + inductor part a little easier as that parts no longer sees such a large variation in the effective gain.

Even if just using the 1 OP amp version it would help to use the ADG1209 and not the ADG1208 - just because of a lower capacitance. I already see little need for a 4th gain setting.

Choosing the compensation is tricky. The values shown in my plan are the current state that I got. Part of the capacitors are bodged on, a bit in a try and error way. I currently have a few more small capacitors on there to improve a bit on the stability, but it is still not great. There is also added complication from the driven low side and an intentionally a bit slow response is not too bad for me.

It is tricky to calculate with quite some capacitance from the switches that changes with the gain setting. So the more theoretical way would be from a simulation with a kind of try and error to find a reasonable compromise. A single divider chain would not get a perfect solution, but only some compromise. The best one could get is kind of swamping the switch capacitance with quite some parallel capacitance and than get the same divider ratio for the resistive and capacitive part. Still large capacitors add to the capacitive loading of the op-amp which is not good either.
It is not that bad as in a first approximation for the gains of 1:10:100 without the switch capacitance one would have capacitors in about a 1 :10: 90 ratio, so not too much capacitance to the input.
So one could start with something like 3 pF / 22 pF/ 180 pF. The switch capacitance adds especially the the 2nd capacitor and thus a little larger capacitor at the start. The time constant would still be in the 300 ns range and thus fast enough to get good settling.

Separate divider would make things a lot easier but cause more ground current / capacitance. One could than calculare suitable compensation with a theoretical near perfect result.
One might just accept that the x 10 case gets a bit slower and use only 2 gain settings for the 2nd stage: x 1 for an overall gain of 1 and 10 and than a gain of some 10 for the x 100 overall gain. This would leave the simpler case of only 2 settings for the 2nd stage and thus easy compensation there. 

For my circuit with the input amplifier supply bootstraped this option would not work because of the limited (5 V) supply and output range of the AZ amplifier. The gain of the 2nd stage is also needed get the full output swing. The extra speed is more like a secondary nice to have part. So I don't have that option and need the gain of the 2nd stage relatively high. On the other side I don't care so much about fast settling. So it is a little different situation.

[julian1]

 
One might just accept that the x 10 case gets a bit slower and use only 2 gain settings for the 2nd stage: x 1 for an overall gain of 1 and 10 and than a gain of some 10 for the x 100 overall gain. This would leave the simpler case of only 2 settings for the 2nd stage and thus easy compensation there. 
 

So both op-amp stages would be the same - with selectable 1x and 10x,  to combine for (1x,10x and 100x ranges)?

This is less ideal than combining multiple gain stages to better equalize bandwidth across ranges.
But a 10 to 1 variation is a big win/improvement over 100 to 1 bandwidth reduction.
Only two identical (simple) resistor dividers are needed.
And the capacitor compensation can be chosen specifically.
This seems like a useful compromise point.

[Ole]

Hello there,
does anyone have experience with using an op amp such as the ADHV4702 or ADA4099 for the main amplifier?

Cheers
Ole

[julian1]

The choice of gnd current compensation resistor for the ref board of the 3458a is difficult to understand.

R419, -15V / 2.67k == - 5.6 mA.

But the constant part of the ref current draw is much lower. The lt1013 datasheet current per op is 0.5mA max. And the op-amp only drives two 70k resistors and the 15k temp-set divider.

The ref heater is the largest source of variation in current - although change is slow, per the control loop.

The heater gnd gets its own board header pin/ return path which makes sense.

But the reference board also pulls out a separate +18V heater supply pin, separate from the +18V for the lt1013 (perhaps to ease instrumention/measurement, or else to keep the design open to using a separate secondary winding for the heater).

The lm399 heater is nicer, given one can just divert the variable heater return path to the negative supply rail.

[Kleinstein]

I don't see an obvious problem with the ground current. The current to compensate is the zener current, the 2 paths with the 70 K resistors, the 15+1 K divider and the LT1013 neg. supply current.
I have not checked the numbers in detail, but I don't see a big difference.  There would be a slight chance that HP has a mix of versions and R419 may change depending on the revision (e.g.different set temperature). The LT1013 supply current may also vary a bit. So ideally one would adjust the ground current compensation (e.g. with a 2nd resistor in parallel for fine trim).

Compensating the ground current from the rather high -15 V supply is not ideal, but the 3458 design is not really made for low power.

Because of the possible variations the heater current is separate and thus no need to compensate that current, just a separate ground path to the supply star ground.

Is there a plan to include a LTZ1000 circuit with the DMM PCB ?
Ideally it would be nice to also have a 2nd 7 V reference to at least detect sudden / large drift (e.g. like with Datron 1281, 1271, 4950).

[julian1]

You're right, I think forgot the ref zener current. 0.7V / 120R ~= 5mA

[julian1]

A second ref for artifact calibration, and additional checks is a good idea.
Calibrating against the same ref used to derive ADC reference currents doesn't make a lot of sense. 
I don't think anything changes much for ACAL which is all transfer orientated.

[Kleinstein]

For the ACAL part, to check the amplifier and divider gain it absolutely makes sense to use the same reference for the ADC and the test points. This takes out much of the reference noise and the ACAL part can be relatively fast. Similar for the ADC gain the same reference is a good choice.

The main reason for a 2nd reference is to also check for drift or jumps in the reference. It is not very likely to see jumps or strong drift, but there is a small chance to have a misbehaving part (e.g. a bad joint, contamination, leaking metal can). For a test board having space for 2 types of reference would also allow to start with the simper reference for the first tests. Just for the frist tests the 2nd ref. is not such a big deal - this would be more a thing for more reliable / longer cal intervals. If really needed the 2nd ref. could also be external.

Another point that can make sense for the ACAL part and with CMOS switches it is also not that much effort is to have test points with both polarities. So the high voltage divider would be tested with +10 V and -10 V. One would get two results for the divider ratio, that ideally should be the same. This adds a kind linearity and plausibility test and the average of the 2 ways can also reduce the INL effect on the result. Similar the amplifier gain could also use 2 test points. Due to the low effort it is definitely a part to add. An external signal would be more problematic due to the reference noise.

[julian1]

There is already a lt1021/7V (5ppm/C, 1ppm pp 0.1-10Hz) as a direct substitute for the primary ltz1000. It is included as a low-fuss path to do functional tests, without needing to mess with the ltz1000 circuit.

If a second (third) reference was added, then perhaps another lt1021/7V would be enough for basic sanity checking? I like the lt1021 because it is 7V and an uncomplicated soic-8, and there's no need to mess with heater currents like the lm399.

Datron 4950 and 1271 use ltz1000 + lm399 (0.5ppm/C, 7uV pp 0.1-10Hz ?) according to Marco Reps' recent teardown. (Edit). While Datron 1281 has two ltz1000.

There's enough board space, and I experimented with adding a second ltz1000 ref, on the basis that the opportunity-cost in terms of time/cost/complexity is low - since it can be left bare if not wanted.

But I am now thinking it is still overkill and to remove it in favor of a second lt1021/7V. The extra confidence guarantees (long term drift?, noise checks?) and convenience are marginal. And an external ltz1000 ref board (or several) would perform better for calibration-like validation/tests.

[julian1]

The bipolar 10V/1V DC source was added a while back, because of the possibility of an INL-like test. The divider ratios should be preserved because the bipolar voltages are muxed through the same divider (even if the bipolar voltages do not invert around 0V).
So it's really useful - apart from enabling a transfer cal of the HV divider.

[julian1]

It feels like going off into the weeds, and a bit unnecessary. But several configurations are possible with lowish effort (eg. pick your poison).

- lt1021/7V as primary, for quick setup and tests and avoid a complex ltz1000 circuit completely (most useful).
- ltz1000 as primary, and lt1021 as optional plausibility/check reference (like Datron 4950/ 1271) (easy, given lt1021 already available).
- 2x ltz1000 (like Datron 1281). (aid to identify drift/divergence, possibly valuable)

[Kleinstein]

For the start I would not worry too much about a 2nd reference.  It is pretty low on the priority list, especially not needed for the 1st test. There it is more about having the option to start with less than an LTZ reference for the 1st tests.  Besides the boad space it would also be about having a free channel at one of the MUX. With only a voltmeter there are likely some free input paths anyway. With a full DMM with current ranges it depends.

[iMo]

I would not recommend the 1021 soic.. It is a low cost vref (good for 4 digits imho), with potentially large hysteresis in epoxy, etc. With your high-end front end and your 8+digits goal there are two "cheaper" vrefs I would think of only - the ADR1001 (you get 7V, 5V (-5V), 10V out of it without messing with any expensive resistors, planned release Q4/2023 afaik) and the 399/1399 as the "second" reference. The expensive LTZ1000A solution as your external ultra stable reference..

[julian1]

I managed to do a board with sufficiently few silly mistakes, to make it worthwhile to add components and do some tests,

Some waveform pics of precharge/AZ switching running in a state-machine -

first pic - uses a contrived sin-wave as signal input.  And shows the digital pre-charge switch ctrl-line level shifted to the signal/boot voltage. It seems to work quite well over the +-10V input rage.
second pic - shows a test modulation of the precharge / AZ switching scheme.  the precharge-switch selects the signal for the hi-sample, and then switches to boot to shield/protect the signal, when the AZ mux switches to take the lo sample.

The mux organization is changed a bit to handle all the inputs.
The two hi-mux's select the continuous signal of interest, then follows the pre-charge to select signal or boot, then the AZ muxes between the precharge-output and lo/zero signal.

I want to add a mode to test the pre-charge switching to reveal charge-injection bias in the same fashion as the previous tests done with the standalone '4053.
To do this a charge-capacitor (depicted on U402) can be switched onto the signal, so that AZ/PC switching can accumulate a charge, to be measured after a fixed duration/number of cycles.
This would form a useful self-diagnostic test, to run without any operator action.
The DC-source could also generate the signal inputs with a DC bias (eg. -10V,0V,+10V) to validate.

I chose to try surface copper-fills for soic-8 guarding rather than ring traces. At BOOT potential for hi muxes/precharge swtich, and gnd for az switch.
This is simpler due to how related signals get grouped by the 1ofN muxes, compared with discrete jfets placed about the board.
But it can be changed if needed.
I don't think the extra capactance due to the increased copper surface area is an issue. R405 can unload the BOOT driver output if needed.
The trick is to route signal placement carefully, to avoid any capacitive-coupling to the wrong copper fill.

Some schematic comments are more self-notes and are not reliable.

[Kleinstein]

The scope waveforms look good so far.
The signal switching still does not look ideal: there are quite some CMOS switches in the critical signal path and thus possibly a higher leakage current than needed. Instead of parallel MUX chips and using the OE pin one could better cascade them, so that the less critical signals (e.g. the ref. levels, temperature,..) go through one more chip and only 1 mux chip for the leakage critical paths.

With the MUX before the precharge circuit and bootstrapp buffer the bottstrapping of the zener clamps is only working when the DCV input is actually selected. With a different input selected the input could see a little extra input current. It is not ideal, but also not too bad as the input can be isolared via the FETs from the protection and the extra relay

It is a bit strange to have 2 x PV coupler in series. Most of the PV couplers give some 6-9 V out and thus sufficient to turn on the FETs. The voltage is already limited by the forward direction of the photodiodes.
The ohms sense inputs should have something like fusible resistors at the input, before the GDTs. So in case the GDTs conduct the resistors act as a fuse.

Connecting the ACAL signals directly to the input is nice to include all the protection, but it kind of defeats the protection. So ACAL would need the user to isolate the input.
For the ACAL part for the divder (+-10 V or GND to the divider) one could use the same relay as to connect the divider. So the divider would either see the input or the ACAL signal.
The ACAL signals for the normal input already have a path through the CMOS mux chips.
The Ohms ACAL signal would go directly to the amps part - so the relay K401 is not absolutely needed. It can still help to avoid the leakage to the FETs effecting the input inpedance.
The capacitor at the input to check for input bias current is a good idea. One may not need than much capacitance. To measure up to some 100 pA a capacitance of some 1-10 nF is sufficient.