Analog frontends for DMMs approaching 8.5 digits - Discussions

[julian1]

The signal switching still does not look ideal: there are quite some CMOS switches in the critical signal path and thus possibly a higher leakage current than needed. Instead of parallel MUX chips and using the OE pin one could better cascade them, so that the less critical signals (e.g. the ref. levels, temperature,..) go through one more chip and only 1 mux chip for the leakage critical paths.

I debated whether to have the two muxes in series or parallel.  My feeling was that keeping the input series-resistance the same for the various inputs (even if dedicated to secondary importance signals) was the lesser evil. Particularly as it might affect the distribution of charge-balance during PC switching.   Although thinking some more, the secondary-importance signals will be lower-impedance inputs anyway (refs, TIA, TEMP etc) so it matters less.   

3458a has many parallel jfets for input muxing, although that probably reflects the component choices available at design time (no low leakage/multiple-throw switches) .

If the parallel hi-mux organization was kept, an additional relay could work to switch between them. This would remove all potential leakage from secondary inputs, unless actually selected.

max328 should probably be used for the muxes. But their price is annoying, and couldn't be justified for initial tests

It's not clear if a charge-cap for charge-injection tests, or leakage tests as you suggest, could work without another parallel mux/relay. .

With the MUX before the precharge circuit and bootstrapp buffer the bottstrapping of the zener clamps is only working when the DCV input is actually selected. With a different input selected the input could see a little extra input current.
It is not ideal, but also not too bad as the input can be isolated via the FETs from the protection and the extra relay

I hadn't considered this. DCV could be at +-11V from user terminal input, with the selected mux input at 0V and BOOT at the same voltage.
That isn't very good for leakage.
Even with the protection fets switched off, fet leakage is in the order of nA, so they won't help much.

It is a bit strange to have 2 x PV coupler in series. Most of the PV couplers give some 6-9 V out and thus sufficient to turn on the FETs. The voltage is already limited by the forward direction of the photodiodes.

I found the measured PV voltages to be a bit on the low-side - around 6V with a single opto-coupler.
From memory, I made a judgement to use two, based on an actual RDS(on) measurement of the fets at the driven gate voltage, but don't remember the detail.  Cost of the extra part is marginal, although maybe it looks too unorthodox.

Connecting the ACAL signals directly to the input is nice to include all the protection, but it kind of defeats the protection. So ACAL would need the user to isolate the input.

Yes. I really like the idea of feeding in signals right at the front. And am not sure about duplicating them again at the input muxes. Being able to run ACAL/diagnostics without the user having to worry about the state of terminal connections would be nice.  So perhaps more relays are justified.

For the ACAL part for the divder (+-10 V or GND to the divider) one could use the same relay as to connect the divider. So the divider would either see the input or the ACAL signal.

This means one doesn't get the DC-source (+-10V, GND) right at the input, that could be useful calibrate/do self-diagnostic tests for the protection/fet leakage. But it frees a relay that could isolate the input terminals to keep protection active, and so the operator doesn't have to do it, during acal.

And it could isolate the terminal input, when non-DCV inputs are selected via the muxes.

schematic pic added for clarity. 

[julian1]

With user functions, acal, and test-diagnotics there are a lot of mode combinations.

It is tempting to err on the side of caution, and add extra relays as needed, not to screw something up. On the other hand perhaps this relay arrangement might achieve a similar result, with one less relay.

Does this schematic match what is being proposed?

[Kleinstein]

The PCB may not be perfect, but it could still be usable and good enough for tests. If looks like it is porpulated to a large part already. A possibly new version would be a bit later.
Chances are there will be more points to learn from the 1st prototype.

I agree that the max328 is a bit expensive. The  mux508 or ADG1208 should be OK for the tests.
The leakage specs with the CMOS switches (and MOSFETs) are to a large part test limits. Especially for a prototype / test version the typical values are more relevant.

The 3458 has quite some JFETs for switching, but when doing the critical measurements, there are not that many that are relevant as there is 2 stage switching (Q15) for the less critical signals.


Connecting the divider to the +-10 V ref signal when not in use does not interfere with using the signal for other purposes. The 10 M load has some effect on the voltage, but it would be connected in essentially all uses of the reference. I found it usefull to have a separate, less critical MUX (e.g. DG408) for the ref signals (e.g. +-10 V, +-1 V, +-100 mV, GND,... ). This way the cascaded structure for the input switching comes naturally.

For the protection MOSFETs 6 V gate voltage should be good enough. There is no need to switch them on really hard. A few more ohms of Ron are not an issue and this helps to speed up the turn off.

The last sugested relay circuit looks more like what I would suggested.  Not so sure about the ACAL part with K404 though. This would be OK to link to the current part to do ACAL on the ohm sources.
The plan as shown does not include a direct path the voltage ACAL to the input (one may get away with this). The main point may be a check with a short directly at the input to include all thermal EMF, including the 1st relay.
Another point may be using both available contacts in series in some places to get a higher withstand voltage.

[julian1]

I did some DC hi-pot experiments with the passive side of the input protection.

The IXTY1R4N120PHV  DPAK fets are ranted at 1.20kV. With a trip-current of 250uA,  VDS breakdown was measured at 1.25kV with a slow 20sec. ramp.
Pretty much as expected.

GDT are Bourns 2039-110-BT1LF.  They have a rated DC Sparkover at 1.1 kV. The value was chosen to be low enough to protect the fets, while still permitting/withstanding a 1kV potential, with some margin for tolerance.

The GDT are surprisingly small - smaller than some low-voltage 75V TDK ones I have. And they also don't light up on discharge unlike the TDK which I find a bit odd.
One example measured a sparkover at 0.94kV
a second example measured 0.95kV.
Quite a bit less than the rated 1.1kV, so this looks funny.

To rule-out issues with the hipot tester, I measured the output set for 1kV with a Fluke handheld DMM, and got a reading of 1.04kV, a 40V difference.
A bit out of calibration, but not that bad.
The current measurement looks right at 103uA, which would correspond to 1.04kV on on the Fluke 10M.

The MOVs B72214S2621K101, are rated at 825 VDC, varistor voltage 1kV, and clamping voltage 1.65kV.
In practice with a trip current set to 250uA, I measure 0.94kV / 285uA leakage.


When put in a circuit configuration, the MOV leakage and resistors should hold the base of the inductor/GDT at GND potential, when not under over-voltage condition.
When GDT sparks, its withstand/resistance drops as the discharge becomes and arc/plasma, and then the MOV withstand-voltage becomes relevant to disipate the current.

After putting parts on the board, I expected the GDT to spark-over at the same voltage (0.94kV), as tested in isolation.
But it actually withstands a measured 1kV output which I find quite odd.

Above 1.1kV there is some noise under the high voltage tension, like the GDT is temporarily/partially firing.
And at 1.3kV the hipot trips for a higher current (5mA ).

[julian1]

I should have looked more closely at the GDT datasheet, they are not precision devices!.

Bourns 2039 DC Sparkover ±20 % @ 100 V/s .
https://au.mouser.com/datasheet/2/54/BOUR_S_A0009095386_1-2539056.pdf

I will also experiment with a lower voltage MOV, so that when the GDT sparks, the MOV will take more of the current. 

[julian1]

I looked at a few GDT datasheets. 
Most parts seem to be +-20% tolerance.
To support a 1kV input, a GDT with rated spark-over of 1.2kV (or a bit more) would be needed.
And to avoid avalanche mode, the fets would need a VDSS of 1.4kV/1.5kV, to withstand GDT part tolerance on the positive side.
But these are a bit rare in DPAK, and a package change may be needed.

Furthermore, some GDT datasheets give more information for faster HV discharge events, for 100V/us, as well as more commonly quoted 100V/s figure,
The faster voltage event has a higher spark-over voltage. eg.

                                 100V/s  100V/us.
GTCA28-122M-R03 1200V    1900V

So I think this is also a nudge toward using larger fets.

I am somewhat confident the optocoupler gate drive can drive larger fet gates.
The most recent test showed a <=1us engagement with only 20V OVC, achieved by removing some (silly ) RC left before the zener clamps,
and by directly probing the isolated fet gate to source.

The zeners themselves will clamp the voltage Ok to protect the inputs on the fast time-scales.
But the possibility of damage to the fets exists if voltages exceed datasheet maxes. 

[Kleinstein]

Getting protection to 1 kV and ideally also higher transients is hard when one also wants very low leakage and very low noise (not too much resistance). One may have to compromise a little between protection and noise / precision.

One point I find odd is the inductor in series to the GDT - the inductor makes more sense in the input path, possibly behind the GDT, to slow down the very fast transients and reduce EMI. Extra impedance in the path with the FETs limits the peak current, at least for the time until the GDT fires. Most MOSFETs can withstand some transient break through with limited energy.
As FETs may fail short it would be a good idea to have some secondary protection as backup, something like PTC or fusible resistor (or both). Still more elements in series add potential thermal EMF. So it is a compromise between protection and precision.
The Keithley 2001 uses 2 FET pairs in series for the protection to get better protection. The K2002 and 2000 use only 1 pair.

The PV optocoupler should also be OK with a larger FET gate. They can usually deliver a few µA and the gate current is more in the nA range, possibly more from the protection zener than the actual gate.
The FET case is anyway a bit tricky, as the pins are often too close togehter to really reliably isolate the high voltage.

I used the small DPAK for convenience and in my circuit accepted a lower maximum voltage.  A reduced design voltage make things a bit easier with the protection and also the relays.

[David Hess]

Getting protection to 1 kV and ideally also higher transients is hard when one also wants very low leakage and very low noise (not too much resistance). One may have to compromise a little between protection and noise / precision.

Oscilloscopes use like a 470k series resistor before the shunt protection and then control noise by bypassing it with about 1000 picofarads of capacitance.  This sort of thing is also common on multimeters, but of course the noise is still a problem at low frequencies.

For moderate voltages, a small high voltage (120VAC) incandescent lamp can operate as both a series PTC thermister and fuse having the advantage of low resistance when there is no overload.  Very sensitive oscilloscope inputs may also use this method.

The least common method I have seen is a pair of anti-series high voltage depletion mode MOSFETs to limit the current before the shunt network.  Like the lamp this has the advantage of low series resistance until overload occurs.

Electrometer designs have high supply voltages available for bootstrapping their input buffer, and this can also be used to bootstrap the input protection to remove leakage through the shunt protection.

[julian1]

I did some reading around fets and over-voltages, and the avalanche figure and 'avalanche rating' are the interesting figures/parameters.  It is a topic of interest to smps design. 
The series inductors to the fets, indicated with 100u (may need 1000u) will limit current rates.

Perhaps the GDT series inductors (1u) were intended to ensure that once the GDT goes active, they stay on for a period.
They appear dropped from later HP designs.

From a practical standpoint, I realized DPAK will fit in DPAK2 footprints. So part choice can be defered to assembly, rather than be baked into the pcb.
Although the smaller DPAK footprints part tidier.

There are some quite small and PTC devices, but thew are only low-voltages.

[iMo]

....,,
..Perhaps the GDT series inductors (1u) were intended to ensure that once the GDT goes active, they stay on for a period.
They appear dropped from later HP designs..

I think putting any L in series with a protection device wired in parallel with the input wire will simply cause the rising edge of the transient will propagate into the input and not fire up the protection device (as the L will block the rising edge from entering the protection device)..

[julian1]

....,,
..Perhaps the GDT series inductors (1u) were intended to ensure that once the GDT goes active, they stay on for a period.
They appear dropped from later HP designs..

I think putting any L in series with a protection device wired in parallel with the input wire will simply cause the rising edge of the transient will propagate into the input and not fire up the protection device (as the L will block the rising edge from entering the protection device)..

Yes, they should be omitted.

[julian1]

I just noticed max328 (octal 1ofN) switch is not available in 'normal' narrow soic-16, so I can't easily test it.

Instead, the footprint options are - wide-body soic-16 which are huge and don't support substitutes/swapping, DIP, and narrow pin-pitch footprints that do not allow pin guarding.     
It would be nice to avoid the design being pushed into using legacy-like footprints.
Some alternatives for muxing the three main critical inputs (dcv, 4w-hi, other) are -

- use 4x spst. max326, that comes in normal soic-16. and which I already have.
- use dg508, adg1208, in normal soic-16, that promise 'low' but not 'ultra' low leakage.
- use jfets. easy availability, and lots of part choices,  mmbfj201, mmbf4117 etc.
- use relays. two small agn200 relays, can mux the three inputs (dcv,4w-hi,other).
- MUX36S08 is narrow pitch only.

Probably the AZ switch itself, is also a candidate for using max326, or jfets. although leakage there is likely to be linear with the single hi input signal.

Perhaps there is some other stand-out consideration that might influence part choice?

I couldn't find much real-world data on leakage, so I have made some simple prototype pcbs for quick tests for cmos versus jfet choices.

[julian1]

Another possibility would be adding a single low-leakage series jfet placed between two series CMOS muxes. 
This would prevent lekage currents from secondary-importance signals switched by the first mux, finding their way to the primary hi-mux for dcv,4w-hi.

[Kleinstein]

Leakage data are tricky. There is often a big difference between the spec limits (= test limits) and the typical / real world leakage. Tight tests seem to be expensive as it just needs time (so that DA can settle) to measure pA range currents. So cheap parts often have loose specs. This applies to CMOS and JFETs as well.

Separating the singls into critical low leakage signals and less critical ones is a good idea. There are usually only a few critical signals and thus only few (e.g. 3 -5) really low leakage switches needed. The less sensitive signals (e.g. the ACAL levels, shunt signals, buffered signals,...) can than use normal / cheap CMOS switches like DG408 / DG211 or even HC4051 for some signals.

JFETs should have essentially no leakage when on, as there is essentially no gate voltage. They still need more effort with the extra gate signal and things like a LM339 as driver. When off the leakage is expected to be an about constant current, with little dependence on the voltage.  CMOS may be a bit lower leakage when off, but can have gate leakage when on. In addition there are the protection diodes.

Some of the leakage current can also compensate. In some cases DMMs have additional JFETs for clamping towards the positive supply, that also compensate some of the current.

The bootstrapped pre-charge circuit should give an essentially fixed leakage current, as the supply for the chips is bootstrapped and thus fixed conditions. So far the leakage I have seen was low ( ~ 5-10 pA), though the specs for the LV4053 are not tight at all and allow much higher leakage. Of cause the leakage can vary.

In my concept I have 2 points to reduce the switching a little:
1) I have not MUX befrore the precharge part and thus 2 seprate precharge parts for different sources ( voltage inputs).
2) The high voltage divider has a seprate AZ amplifier as buffer and thus changes form a rather sensitive signal to a non critical one for switching.

[julian1]

My plan was to use MAX328 as the obvious lowest-leakage/convenient form-factor part, and call it done.

But it's probably worth taking a step back and considering the design principle,

It's a good point about the bootstrap precharge/ switch leakage. This circuit really determines the order of/budget for permissible leakage for anything else built around it.
I will test it again, since the previous isolated tests were more for charge-injection
Probably both input and output leakage tests are needed, to include gate,supply/cross switch leakage.

And then test some analog switches/jfets, to see how they compare.

For critical signals - the hv divider, and DCI/current for low-current ranges if no TIA is used should probably be included.
With the effort put into the AZ front-end, it probably makes sense to use that in preference to adding AZ op-amps,

Modern DPDT relays have the possibility to mux both sides of a signal, into the AZ mux eg,
  - 4W hi, and 4W lo on one relay.
  - DCV  and LO. on another.
  - DCI-HI and DCI-LO on another relay.

And this might help cancel thermal/EMF offsets on the disjoint metals used in relay construction.
Although the input selection path already includes single-ended relays and a terminal gang-switch, so it's not clear if there is an advantage.

Including an input-path - with only semi-conductors - to be able to measure the thermocouple offsets of mechasnical components - as you already pointed out is a good idea.

[julian1]

Actually I think the front/rear gang-switch is double-ended (switches hi and lo) so (potential) thermal-couple effects should be cancelled, provided no strong board temp gradients.  And for current it doesn't matter.

[Kleinstein]

With latching relays I would not expect much thermal EMF from the contracts, as the thermal gradients are expected to be small. It is also not at all clear if the 2 contacts see a similar gradient / difference and thus could provide compensation. Compensation works nice with 2A type reed relays (e.g. input of the 34401, 3458).

Using an AZ op amp as a buffer for the divider is relatively easy and comes with a nice side effect.  An AZ buffer can be quite easy, in my case an MCP6V76 and TL061 and a current source. The buffer is not replacing the main amplifier, but an alterternative to critical switches and the pre-charge part (if used individual per input). The divider (e.g. 100 K resistance or more for a smaller divider ratio) already has quite some noise. So there is no problem in having a buffer with a noise in the 20-30 nV/SQH range. The non standard option that one has with a buffer is to use not just a classical divider, but a kind of hybrid with an inverting amplifier / active divider. The output of the buffer is inverted with a not so critical inverter and the divider is than not towards ground be towards to inverted signal. This way one gets a positive and inverted output signal and effectively doubles the range for the signal input. In addition the input is sampled essentially all the time even in the AZ mode. This allows for a lower noise (some 30% less) even with the same divider (e.g. 1 :100) and even more (50% range) with an adaped (e.g. 1:50) divider to make use of the large signal range.

For the bootstraped precharge part the through the switch leakage should not be critical. The 2 switches there see essentially no differential voltage (only the offset of the buffer). Bias on the output side of cause is part of the input bias.

[julian1]

I did some stand-alone switch leakage tests.
Current leakage to gnd of the analog-switch (adg1208, dg508) output was measured while applying a high-z, +10, -10V voltage to an (open/off) input pin.
The results are quite good,

adg1208
measured rds(on) 111R
fixed  leakage, around 0.5pA .  (copper guard was left floating, so leakage from board pwr/ctrl pins to guard is possibility, not just internal fet gate/protection diode/substrate leakage),
+-10V on input gives +-0.5pA. change in output current after allowing maybe 20sec for settle time.

The behavior is the same - whether all ctrl pins are lo - or if EN is hi and an unused input pin is made active.
This indicates the EN pin works as logic only, and doesn't control some global extra internal isolation fet.


dg508. maxim/AD.
measured rds(on)=295R.
around 1pA fixed leakage (guard left floating, so leakage from board pwr/ctrl pins is possibility),
and +-10V, gives maybe +-0.1pA current diff on output. very hard to measure.

I have max328, but probably won't test it, as it would require a better setup / DUT shielding, and automated/scripted operation.

But, I think it is enough information to favor usinig them versus or jfets/relays, given that -
Ib of the guard buffer is already expected to be around 1pA.
And the floating pre-charge switch leakage is expected to be higher still.

The input relay muxing has been reorganized for improved terminal isolation during ACAL function.
This has the added benefit of reducing leakage/non-linear affects of leakage into the critical hi-mux.

Currently when a specific DMM function/mode is *not* active - the signal present on the input pin corresponding to that function is held high-z, at boot potential, or else attenuated.
   
Currently -
- when DCV is not used, input relay k405 is open, and output is held at boot potential by the input protection (via bootstrapped clamp diodes).
- when secondary-importance/buffered signals (refs, voltage-source, tia) signals are not used, the second mux output is held at boot potential (by muxing BOOT on its input).
- when DCI-HI is not used, the current input/protection/acal relay is open (K702, and ohms-source-relay) and output is high-z.
- when DCV-DIV is not used, K402 is open and output is high-z. exception if using DCV with 10M input impedance - then DCV-DIV is 100x attenuated at the mux.
- when 4W-hi is not used - ohms current source relay is off. exception if operator leaves 4W cabling attached to DUT while in 2W or DCV omde, then the measured voltage is duplicated on two mux input pins . but that is probably an ok edge case.


- A question exists - if the non-active/unused input pin voltage should be switch from the guard buffer voltage to agnd/0V.

So, the DCV could be held at AGND/0V (via the bootstrapped clamp diodes) during current measurement mode - instead of following the guard-buffer for DCI-HI .
Likewise for the secondary-importanace hi-mux, which could be follow AGND/0V, instead of boot.
Even just as a test/diagnostic I think this would be useful.

- There is already some guard switching for current ranges - eg. on shunt-ranges boot/guard follows the shunt voltage, but if TIA is engaged it follows agnd/0V.

[julian1]

To summarize, and try to reduce scope a little, a good simplifying change - would be to at least make the bootstrap voltage on the clamping zeners switchable when the dcv input is unused.
So that the corresponding pin of the hi-mux could be held at agnd potential to reduce leakage effects.
And then similar treatment for the secondary hi-mux, that can mux agnd on input, to keep the corresponding pin of the hi-mux at agnd, when unused.
Most of the other inputs are already high-z when in-active due to switching relays.

[Kleinstein]

If one really cares about super low leakage and use with very high impedance signals it would make sense to pull at least the zener clamps to GND for the unused inputs. Depending on the diodes (Si or IR diodes of an optocoupler) used for the final clamping step this would limit the residual voltage so some +-0.5 to 1 V. I somewhat doubt one would need to really pull the input to GND. Some signals like the divider would be at essentially GND anyway. So it would be mainly 1 or 2 inputs. to worry about.

For the secondary mux one could choose a signal close to GND (e.g. low shunt or 100 mV ref level) to get at least a fixed amount of leakage.

Leakage currents in the 1 pA range looks really good. I don't think this should give problems for a more normal DMM input. After all this is not an electrometer input.

[miro123]

I noticed, that some confusion comes from mixing up two different concept.
1. Old fashion dual/ multi slope, where processing mostly analog in nature, so problems with absorbtion & charge injection  was dificult to resolve.
2. Modern SD ADC, ad7177 etc (I'm experimenting with max11270 & mcp3562) - here we shoudn't care about injection & switching whatsever noise since it's much easier to throw  a sample taken rigth after switching and take another one after long enough settling period, 1 millisec or so. Counting to get 1 kHz sampling rate high just above most OPA +Voltage references   1 / f corners. So requirements to switching IC is close to non - any cd4043 is good.

I've read the whole thread 6 pages. My short summary "Echo88" started this thread giving  an solution related to your second point (modern SD ADC). The whole thread went in cogently other direction as topic starter (old fashion DMMs)

My question is does somebody works on AFE for modern SD converters?
My epxeriance in this areea so far.
1. Build AFE based on PGA280 coupled to ADS1256 - that was good first time experience, but I run to the limitation of this simple design
2. Evaluated ADS125H02
3. Looking to do  AFE based on HPM7177. Idea look straightforward, but I don't like two thinks
  - Using 8 of precisions resistors - yes some of them cancel the TC effects, but still a lot of dependency /cross correlations.
  -Applying raw power to solve TC issues - It is great solution for CERN, they run in lab environment, no huge ambient temperature deviation. Peltier oven works fine for them
4. Using THS4551 or THS4561 LTC6363- They have limited  DC perforce in single IC AFE configuration, but they delivery the BW needed to drive modern ADCs.
  Questions
- How can I create outer DC stable loop around those FDAs/THS4551,4561,ltc6363/? Can I reduce the number of precisions resistors used by HPM7177 design
- Do I need to start separate thread - related to AFE for modern ADC?
Greetings,
Miro

[Kleinstein]

The front ends for a SD ADC chip and old style multi-slope ADC are indeed different. It is not so much about switching / charge injection, but the voltage range. MS-ADCs are usually build to work with some +-10 V input range relative to a ground. The SD chips usually have a differential input and some types need true differential drive to use the full range (e.g. +-5 V). Even if not needed for other ADC chips, differential drive may help with linearity.  There are a few common points with the protection and input switching, but it is more like a separate topic and maybe worth a seprate thread.
Another point needed is the ADC drive part - which is not easy and can effect the INL.

The PGA280 looks nice for a relatively simple solution with maybe 6 digits, but there are some limitations with the input bias and linearity to really reach the high end.

There are alternatives to the HPM7177 design and some should get away with fewer precision resistors. The number of precision resistors needed by itself is not that bad - the question is here if there are of the shelf suitable resistor arrays available. The HPM7177 design is with a signle range - with additional gain settings things I see more complications.
My DMM design with an AZ amplifier at the input is somewhat suitable to a differential ADC, but it would not add attenuation. So the range would be the same of smaller than the ADC input, so +-5 V (and smaller ranges) for the AD7177 or similar. On the upside there are no critical resistors for gain 1.

DC stabilizing a fully differential amplifier could be tricky - at least I don't see a simple way. The typical differential gain circuit with low input impedance is anyway a bit limited for high precision and they need 4 precision resistors for 1 amplifier.

[Echo88]

The number of precision resistors in the HPM7177 is rather low: 2x PTF56 + 3x S102K for the LTZ1000 and some networks for the input divider and ref divider. In my case TDP1603 are used instead of Vishay PRND.
I havent yet tested my version fully and it will take a while.
I also dont really know a way to use the THS/LTC6363 in a composite design, i rather use the proven drivers from the HPM7177.
Wether a new thread about modern ADC frontends makes sense or not i cant judge.
I assume that this stuff gets rolling again after a proven design gets available as open source for multiple people to test.
Attached is a suggestion from my side, based on the 3458A JFET-frontend with added gain selection based on TDP1603 and ADC-drivers based on HPM7177. Due to two unknown Dual BJT/JFET used in the 3458A-frontend one needs to find some available ones that fit the spec.
Its not complete, does anyone notice obvious flaws or things to improve?

Edit:
Changed guarddriver to lower biascurrent one MAX9945 instead of OPA140 (LMC662 supply range not suitable).
Added 3458A Black Edition original used AFE-transistors.

Heres are the datasheets for most of the transistors used in the AFE: https://edesign.astutegroup.com/wp-content/uploads/sites/2/2022/03/2022DataBook-Linear-Systems.pdf

[Kleinstein]

For the JFETs for a discrete build low noise amplifier the TI JFE2140 should be a pretty good choice now: The offset, input bias and noise are pretty low and it is reasonable available and priced. Chances are one can get away without an extra offset trim, maybe a single resistor to choose, if one wants very low thermal drift. I see no need the the DAC to adjust the offset, especially not with the low offset JFE24140.

The suggested plan has a few odd points: The extra buffer with U5 U9 does not help and only adds noise and possibly a tiny bit of drift. A similar argument applies to U3+U6.
There are AZ amplifiers also at point's where they are not really needed: e.g. U8 for the GND current compensation and the U12/U13 buffer for the 2 nd divider. Here a more simple buffer (e.g. OPA141) would be better (less bias an the first divider).
A suitable substitute for the MC34081 would be the TLE2071 - it also has a common mode range extending to the positive supply, which may be an issue here.

The divider with RN2 for the 100 mV range is rather high resistance. If one is after low noise one would use smaller resistors (maybe 500 Ohm ?) here.

It is not good to use a 1:8 MUX for the gain settings as the unused channels add extra leakage and capacitance. A 1:4 MUX would be the more obvious choice.
The switch capacitance can be tricky and may require at least some compensation capacitors.

The AD8065 with a +-12 V supply should have a resistor at the input for protection in case the stage before goes higher than +-12 V.

A current of 4 mA for the JFET amplifier is way to high for a precision amplifier. This has a good chance to cause thermal nonlinear effects. 4 mA may be OK for a more nV meter. A large range linear amplifier would be more like 200 µA to 500 µA.

The way the circuit is shown the initial part could be the same as for a multi slope ADC. So not really a separate thread for this.
However this way there is no range with no gain/divider before the ADC. So the stabilty of the TDP divider network RN6 would be overall gain quite a bit in all ranges. There is a good reason the HPM7177 uses the expensive custom resistor arrays for the divider stage.
A front end planded directly for the ADC chip would have a 5 V range with no gain / dividers and then maybe a 12 or 20 V range with divider and maybe 500 mV and some 100 mV with gain, but no divider. This would than be a different type of front end. So not so much inspired by the 3458, but maybe more like the SDM3065.

[iMo]

Would be great to design, as a POC, a simple +/-12V input front-end only (capable say 7.5digits). It will satisfy 90% people here, as most of us want to measure their references only. After some practical evaluation by the experts here, the next step could be adding more ranges, and other functionality, etc.
A rather complex design with many exotic parts might end-up as a single prototype gathering dust, as people will not be able to reproduce it..