Analog frontends for DMMs approaching 8.5 digits - Discussions

[julian1]

The schematic helps clarify that the signal/precharge switch works as an independent module. And that it can be switched independently of the signal/zero switch if needed for testing purpose.  Also how a current mirror and common base pnp, can work for the floating switch control.

The cap for the complementary driven charge compensation is tiny. which is very promising. It seems like a real advantage of jfets (versus muxes) if charge-injection can be simulated.

The adjustment of the gate charge compensation via C5  could be a bit tricky for 2 reasons:
1) it may not be easy to measure the small transients - ideally not much reaches the input.

Presumably one could check the effect and perform trim with reference to AZ/no precharge measurements - with some averaging over time - due to extra flicker noise without the AZ switching?

A general question about jfets - do the two actions of turn-on/pinch-off when performed in sequence tend to cancel the gate charge injection?

Possibly the complementary trimmer cap approach could also be applied to a cmos mux, to provide fine trim.  I noted, the ltc1043 datasheet states that the chip is trimmed so internal nmos and pmos charges balance when signal input is at 50% of VDD.

This suggests there might be a general possibility to trim nmos/pmos relative contribution in a cmos mux  -  by trimming/offseting the bootstrap VDD slightly to the signal (eg. probably signal near 50% of VDD or near GND)

[Kleinstein]

Many of the CMOS switches are internally compensated for a small charge spike. The gate capacitance for both JFETs and MOSFETs is somewhat nonlinear and the compensation is thus often only good at a fixed voltage. The more practical way to trim the charge compensation for a CMOS switch in this application would be via the supply relative to the signal. At which voltage the charge injection is near zero depends on the chips - it can be in the center or at one end (often the neg. side).
3 possible candidate chips would be be ADG633 and TMUX1134, maybe max4053. 1/3 of 74LV4053 may work, but the leakage specs are very loose - so testing / selection needed.
I am not sure if a CMOS of JFET solution is better. For the CMOS switches I found it surprisingly difficult to find suitable ones with low leakage, low charge injection at the same time. Especiallly single switches tend to be rather low resistance and thus higher leakage and charge injection.  Availablity is another problem.  With a suitable chip the CMOS solution would be likely easier, with less extra trim needed.

The charges for the turn on and turn off with a JFET should compensate. However the impedance on both sides of the switch determines on how the charge is split to the 2 sides. Another point is that the charge pulse somewhat (the gate resistor helps a little) follows the nonlinear capacitance: on turn off there tends to be more current at the start of the transition and on turn on there is more current near the end. So for the point between the 2 JFETs the overall charge can compensate but there is still first current flowing out from turn off and then later current in the other direction. So even with well adjusted compensation there are transient with charge flowing in and out, even if the sum is zero.

For testing one can use a much more frequent switching (e.g. kHz range instead of some 2-25 Hz for usual AZ cycle), especially for the current. This initially confused me in the simulation, as there I had a much higher frequency and thus more current. For the individual spikes a test point with less filtering may help, though is can also acts back and effect the current.

[dietert1]

Kleinstein, concerning the schematic you posted for input protection: Do you have measurements on thermal EMF offsets generated by the mosfet pair? Probably the mount/geometry makes some difference. Maybe board cut-outs to reduce temperature gradients?
Also i remember another schematic from you with additional bipolar transistors to speed up turn-off (faster than through optocoupler). Is there a reason they disappeared in the current proposal?

Regards, Dieter

[Kleinstein]

The circuit without the extra BJTs is too keep it simpler, but one could add them. Under normal conditions the BJTs I have on my PCB do not engage. They are more like a back-up plan, if the optokoppler is a bit slow. Ideally there is some LC filtering (thus the relative large inductor at the input - this one should allow a high peak voltage) to slow down very fast transients.

With my PCB I have the same circuit 2 times: one paths shows a little thermal EMF effect (some 300 nV AFAIR) and the other shows not detectable extra delayed offset (e.g. < 20 nV AFAIR). Chances are the layout and maybe the way the fets are soldered cause the difference. Currently my FETs are TO252 parts soldered as THT. The 2 paths are a bit different later on (a JFET switch vs a CMOS switch), but I don't think this is the relevant difference.

This is still without extra cut outs. A slight difficulty is the position of the photovoltaic couplers: they should resonable close to the MOSFETs to keep the leakage paths and parasitic capacitance small but as a heat source it should also be a bit away from the MOSFETs to avoid temperature gradients. For highest performance some cut-outs and a little more distance would make sense.
With my PCB I have the resistors for the PV couplers close to the couplers and thus additional heat .

AFAIK the Keithly 2182 nV meter uses a similar circuit for the protection (AFAIK no extra BJTs), but with quite some distance between the FETs and PV coupler.

Another point to consider is that if an input is inactive, it could help to actually pull the input close to ground. An open input can pick up stray signals (e.g. leakage through the MOSFETs). Via non ideal isolation (could be just capacitive) the guard signal could effect the active input. A frist step would be a switch parallel to the zener diodes to at least limit the voltage.

[julian1]

The same approach to jfets may work for Linear Systems dmos sd5400 switches. With slightly high capacitance (2pF versus 0.4pF for j201)  needed to compensate, when switching into a high-z input (like the signal/zero switch + op buffer).

I think the trimmer cap required for such small capacitance values might be tricky.  Mouser has manual trimmers at low values, but they are expensive, and need a (plastic trimmer tool). I found a digital one, PE64904C-Z but it 'only' goes down to 0.6pF. trimmers in series will add extra parasitic capacitance. Simulating using complementary trimmer caps gives odd results.

According to http://www.signalpro.biz/calculators/pcbcapacitance.htm, a 0.5mm trace is around 0.77pF / cm.

It would be good to compare with a cmos mux. It should be possible to boostrap the mux with a trimmable offset relative to the input signal, using an extra op amp/ or discrete bootstrap circuit.

[Kleinstein]

The SD5400 would be a option, though a bit more difficult to get. The higher capacitance is natural with lower on resistance. The 4 pin MOSFETs may allow to use the substrate voltage for the fine trim instead of the capacitance.

If needed one can reduce the voltage of the compensation signal with a resistive divider and than use a larger capacitor (e.g. 1/3 the voltage and 3 times the capacitance). As there is anyway a capacitors to the "ground side", one could also use a capacitve divider. The HP3456 uses a fixed capacitor and a trimmer at the divider.   For fast switching this can still be a bit tricky because of parasitic capacitance at the resistors.

The digital trimmable caps have added ESD protection, that could add leakage. In addition one would need to bring an I2C or similar signal to the floating part.
The size of the gate drive signal could also be used for fine trim, as the gate capacitance is nonlinear. This would also apply the the JFETs.

1 pC of charge injection corresponds to 0.2 pF*5 V control signal. So the specs for the charge injection for good CMOS switches are somewhat comparable to what can be expected from a manual trim. The nice thing is that the gate drive is internal and thus no external inverter and delay. The CMOS chips in question (max4053, adg633, TMUX1133) are mainly available as TSSOP or similar, so quite fine pin pitch. This is not ideal for leakage.

[julian1]

Thank you for your insights, and options for dealing with small capacitance values.
Very good point about leakage for the inputs,
Driven guards should be a feature for unbuffered inputs.
Routing pcb guards for soic and sot23 pins is ok, but there's no chance for tssop.

Package options for cmos muxes
    adg633 and TMUX1133 tssop16,
    max4053             qsop16 (tssop) and soic
    sn74LV4053          tssop and soic

For soic mux, that limits part choices,

max4053
    guaranteed off leakage 0.1nA.  (A version )

sn74LV4053
    datasheet states, off leakage 1uA.  but needs to be tested.

[Kleinstein]

I have the 74LV4053 in the ADC and the leakage there is pretty low (some 10 pA for 3 switches and 2 OP-amps). It is a cheap part, and thus very loose test limits.
This kind of a common picture with most CMOS switches. The limiting specs are pretty loose. Even with JFETs there are only few parts really tested to very low leakage, though the typical specs are OK.
One may have to design with the typical specs here and than select or take chances.

In the actual use case there is very little voltage across the switches and the gate voltage is also more moderate. So the conditions are not as bad as most of the specs (e.g. -15 V gate votlage for JFETs or near full voltage across CMOS switches).

The pinout is so that the pins 3,4,5 ( the 3rd switch) could be used for the switch and pins 2 and 6 could be GND of the chip.  So there is at least guarding to the outside, just not between the switch elements itself. One end of the switch is essentially the guard and than there is one switch enabled.  So no extra guard needed between the 3 pins of the switch.

[julian1]

The pinout is so that the pins 3,4,5 ( the 3rd switch) could be used for the switch and pins 2 and 6 could be GND of the chip.  So there is at least guarding to the outside, just not between the switch elements itself. One end of the switch is essentially the guard and than there is one switch enabled.  So no extra guard needed between the 3 pins of the switch.

That is a fiendishly clever guard strategy, and keeps the choice of tssop open.

[julian1]

For the discrete jfet or dmos option, it may be possible to use a spdt switch to drive the part at the floated signal levels.

[Kleinstein]

Using a CMOS switch chip to control the gates would work, but has 2 down-sides:
1) The charge injection from that chip would couple to the guard signal and this way may add a little to the switching pules. Because of the charge injetion part one may even need some extra protection / clamps, especially for the DMOS chip, that may be a bit sensitive.  With the floating HC14 chip the fast transients are local to the floating part.

2) In the current supply situation the CMOS switches add another part that may have a long lead time or is hard to get.

[julian1]

Thanks. I considered that a non-floating cmos switch would contribute it's own charge injection (varying with input voltage) putting small DC offsets on the gate and compensation drive.  But overlooked they would capacitively couple across to the jfet/dmos.

[julian1]

Here is some data for TI LV4053 v MAX4053A, for a signal conditioning precharge switch.

The switch is driven at a high frequency to try to reveal the bias of the charge injection at different bootstrap rail offsets, and with difference source signal impedances.

And hopefully avoids capturing anything else like the ctrl signal being modulated onto the high-impedance source due to poor PSRR.

There is an issue that the Vos of the op paths is different, and when testing with a DMM we sample continuously - which includes both precharge and unbuffered signal, via the buffer. A real implementation would only sample the signal. But I think it is ok for demonstration, because the op Vos differences get overwhelmed by switch parasitics when switching quickly. 

Code: [Select]


90/10  duty cycle sig/charge
Values are mV.

bootstrap VSS rail          freq
relative to Signal.

                   off     100Hz      1kHz      5kHz

SN74LV4053ATDRQ1 soic

   0V     100k    -0.009    0.013      0.035     0.123
           1M     -0.006    0.036      0.230     0.574
          10M      0.019    0.27       0.23    -6.75

-0.5V     100k    -0.009    0.014      0.050     0.210
           1M     -0.014    0.035      0.375     1.55
          10M     -0.06     0.280      2.17     5.55

  -1V     100k    -0.009    0.014      0.056     0.247
           1M     -0.017    0.042      0.45      2.07
          10M     -0.08     0.33       3.50     14.0

  -2V     100k    -0.011    0.012      0.048     0.212
           1M     -0.19     0.032      0.039     2.23
          10M     -0.102    0.24       4.75     27.4

  -3V     100k    -0.011    0.011      0.031     0.124
           1M     -0.020    0.014      0.230     2.06
          10M     -0.011    0.05       5.66     41.5

  -4V     100k    -0.009    0.008      0.005     0.006
           1M     -0.020   -0.012     -0.012     1.50
          10M     -0.125   -0.215      5.88     52.4


MAX4053AESE soic

   0V     100k    -0.042   -0.029     -0.075    -0.303  (reads a bit high due to op amp temp drift from soldering)
           1M     -0.036   -0.023     -0.071    -0.300
          10M     -0.033   -0.020     -0.068    -0.297

-0.5V     100k    -0.029   -0.069     -0.580    -2.867
           1M     -0.135(?)-0.672     -5.709   -28.43
          10M     -1.049   -6.466    -57.40   -279.0

  -1V     100k    -0.020   -0.099     -0.945    -4.717
           1M     -0.075   -0.981     -9.305   -47.365
          10M     -0.56    -9.267    -84.121  -482.02

  -2V     100k    -0.018   -0.148     -1.473    -7.366
           1M     -0.056   -1.479    -14.451   -72.79
          10M     -0.41   -10.91    -100.17   -716.84

  -3V     100k    -0.016   -0.189     -1.900    -9.512
           1M     -0.043   -1.882    -18.596   -92.042
          10M     -0.300  -10.88    -105.99   -886.7






identical board setup (dual soic/tssop footprint) as previous two tests .

                   off      100Hz       1kHz     5kHz
ADG633  tssop

    0V   100k     -0.005   -0.012     -0.190    -0.987
           1M     -0.005   -0.184     -1.915    -8.746
          10M     -0.005   -1.88     -15.41    -61.5

  -100mV 100k     -0.006   -0.073     -0.778    -3.977
           1M     -0.006   -0.774     -7.681   -38.39
          10M     -0.009   -6.89     -69.24   -354.

  -1V    100k     -0.013   -0.536     -5.3     -26.                                        dec 29. 2022.
          1M      -0.014   -3.090    -30.9    -252.
         10M      -0.020  -14.4     -497.     2417.






[Kleinstein]

An interesting test.  As expected the extra charge injection is best for a low offset in the supply, so close to the negative supply at the switch chip. So one may get away without the extra shift or only have a small shift of a few 100 mV.

The input currents seems to be reasonable low: some 3 pA  with the 4053. The max4053 case may be effected from drift but still looks OK, but somewhat uncertain, as the offset could be different for the 100 K / 1 M /10 M case.

The charge injection caused extra current still looks OK: e.g. some 30-40 pA for the LV4053 at 100 Hz  , so 0.3-0.4 pC of net charge injection. Actual use for DC measurements would be more like 25 Hz (1 PLC). For the max4053 it looks even lower (e.g. 30 pA range at 1 kHz) - but a bit unclear if still drifting.
With relatively little capacitance at the input the charge pulses may cause more of a charge peak that the DMM averages.

So far both switches look acceptable for a DMM input. I would still prefer the max4053 because of better characterization.

There is a chance to get coupling from the control signal. I would not worry so much about PSRR and coupling to the supply, but more about capacitive coupling to the input. With a 5 V jump in the voltage it only takes a fraction of a pF to get pC charge pulses.

Instead of a resistive input, one may check a capacitor (e.g. some 10 nF PP or PS) at the input. The input bias / charge puslses would that slowly charge the capacitor and translate to a drift rate.
This would also smooth out the charge pulses. A full front end would likely have some filtering capacitance (e.g. 20-200 pF range) to ground, also to help with ESD and EMI protection.

[julian1]

Added some data points for tssop adg633, under identical test setup - leakage is perhaps better, but charge-injection worse.

I have another board with a bootstrap variation to trim in both directions (positive to a few 100mV). It may be interesting, now its established that the negative supply is the point of interest (even just for data). More care is needed around board soldering, cleaning, drying before tests.

Agree that some capacitance on the input is needed, the switching is quite spikey, and the bootstrap follows the input, so I could see bandwidth coupled effects.

The suggestion for a cap to accumulate charge instead of input resistors is a great idea, and means that more realistic AZ cycle speeds can be used.

[Kleinstein]

As a last resort one could also shift the voltage used for the precharge. This is done with the HP3457 and 3458 via a DAC.
The charge injection is small and it does not need much shift (e.g. 10-100 mV range depending on the capacitance at the amplifier) to get some 1 pC.
Getting a slight positive shift should be easy.

Capacitance on the input and output side can also effect the charge injection. The actual charge pulse is quite short and the impedance on both sides of the switch can have quite some effect on how the gate charge distributs.  This effect can also be seem with AZ OP-amps:  about equal impedance/capacitance on both inputs can lower the input bias and possibly also the offset.

I first found it strange to have the extra amplifier for the bootstrapped supply (for the switch). Because of the current to the control signal this may indeed make sense.
To reduce at least the fast part of the control current, one could add a RC series element from the raw control signal to the bootstrapped supply. This could compensate much of the fast current part.

[julian1]

The extra op amp was the simplest way I could see to do the circuit. Although I did have in mind the idea of a sum junction for dac control. But it's also possible no adjustment function is required, and just using 0V might be sufficient. Not sure if the boostrap should track tightly (no extra op), or be slowed with RC from the input.


Added a 2k on the output of the switch before the amplifier (R505), to match the input resistor.

Using a 10nF PP cap, to accumulate offset, over a fixed 10sec time period.
Values in mV.
LV4053

Code: [Select]

rail offset     20Hz.       50Hz        100Hz
to signal.

-100mV          -8, -10     -1.8, -7    -2.5, -1.9
-25mV           -4.5        -9          -1, -0.8
0V              2, 1        2.5         2.5
+25             15, 18      13          19
+100            480         500         480

Maybe I am doing something wrong -
But when comparing 50Hz v 100Hz one would expect to see twice the accumulated offset from charge injection with higher switch cycle count.
But that's not apparent from the measurements.
So I think switch leakage (or pcb leakage or something else) dominates at more typical AZ frequencies.

Testing with switch held in fixed state - either Off or On for 10seconds, shows similar bias and magnitude for different bootstrap offsets.

Code: [Select]

                off             on
-100mV          -9, -8          -13, -12
-25             -4.5, -4.7      -7
0               -0.5, -2.5      -0.5, -2
+25             8, 9            18
+100            280             520

The sweet spot seems to be right around 0V.

I can see how to calculate charge injection per cycle - eg. a 30mV range (+19- -9), with 10nF is 300pC of charge.  10 secs * 50Hz == 500 cycles. = 0.6pC / switch.

Is it possible to calculate the inferred current (from leakage or charge injection) from the accumulated charge on the cap?

I still have the 10M/100k paths and can use the voltage drop for leakage current, but a calculaton from the acumulated cap charge may be better.

[Kleinstein]

With 10 nF and a 10 s intervall to look at, 1 mV corresponds to 10 pC. The average current is just the charge divided by the time interva, so 1 pA for 1 mV of drift over the 10 seconds.
The choice of 10 nF and 10s makes it easy to convert to current.

The leakage current from the switch seems to be more important than the net charge injection. There is relatively little difference between the switching frequencies.
The +100 mV case may already see leakage from the substrate diodes.

The net charge injection measured in this experiment is measuring the sum over the turn on and turn off part and for both sides combined.
This is different from the usual charge injection specs in the data sheets. This is only for the turn off part and only the drain side. The charge injetion specs are only a hint on the actual performce in this circuit.

The sweet spot really seems to be close to 0 V. Not just for the switching effect but also for the net leakage.
With the low leakage and switching induced current there may not be a need to have an adjustment of the supply offset.
For just the switch chip the bootstrapped supply can directly follow the input, though it could still be a good idea to keep the short switching spike away from the bootstrapped voltage.

If the bootstrapping is also used for the amplifier than a slow down is usually needed to get stability. The amplifier would normally need both a positive and negative suppply (e.g. +-2.5 V), while the switch is more like +4 V or so. A bootstrapped amplifier would allow for something like the OPA376/OPA377 (or even MCP6286) as a somewhat cheaper and lower bias alternative to the OPA140.
For the switch filtering should not be absolutely needed, but it still makes sense to have some filtering to keep the fast switching spike away from the supply. For just the switch and 0 V offset the buffer for the guard/pre-charge signal could also directly drive the negative side of the switch supply.

[julian1]

Without going too far down a rabbit hole, getting reasonably complete data is useful for part evaluation.
For max4053 and adg633, charge injection is more detectable at lower (typ AZ) frequencies.

Code: [Select]

Accumulated charge on 10nF cap after 10secs in mV.
   
           off      on     25Hz     50Hz     100Hz      1kHz
lv4053.
 
-100mV      -7     -10      -5       -1       -1        +85
-25mV       -3      -7      -2       -2       -2        +55
0V           0       0      -4       +2       +4        +49
+25mV       +9      21      17       20       23        +61
+100mV     270     510

max4053

-100mV      -3      -4      -43      -74    -150      -1500
-25mV       -4      -3      -26      -37     -67       -620
0V          -4      -2      -15      -24     -35       -333
+25mV       -4      -3      -6        +2      -7        -38
+100mV       0       0      +21       41      87        880

adg633

-100mV      -2      -1      -192    -380    -800      -7000
-25mV       -2      -1       -71    -150    -280      -2800
0V          -1       0       -34     -67    -121      -1210
+25mV        0       1       +21     +23     +54       +500
+100mV      29      26       180     330     579       5600


A quick test of the discrete jfet switch approach shows very good leakage.
With J201 and VGS -5V, the offset can be very low. one test got 0.1mV over 30 secs or so..

But the polarity of the switching compensation doesn't match expectation, or ltspcie.
Layout is ok but there is still an unbuffered signal trace near ctrl lines,
So the chance is that parasitic board capacitance is enough to shift the initial bias direction.

Code: [Select]

For discrete jfet circuit with two J201.

varcap not populated
     
           off      on     25Hz     50Hz     100Hz      1kHz
            -1      -1      -18      -33     -55       -520

varcap added (only did 1kHz test)

CCW / barrel screw up                                  -780         
CW / barrel screw down                                 -810         

Adding a 10pF TH (smallest cap I have) bodged on the inverted control signal fixes it. And the polarity is shifted in the desired direction from -90uV to +250uV drop on the 100k at 1kHz.  So the better approach is probably to add small fixed caps to compensate parasitic capacitance in board layout, and then use a varcap for fine trim.

[Kleinstein]

For the JFET circuit the use of the HC02 add a short phase with both fets off. This sounds reasonable, but also effects the charge injection, as the compensation pulses may no longer line up perfectly.
This would be at least different from my simulations. There the gates are used to compensate the delay and get near simulataneous switching assuming a threshold of less than 2.5 V.

With the extra amplifier for the BS supply the capacitors C504 and C514 are going to the supply of the logic chip. So the fast gate charge current would still go through OP-amp3.
At the high speed (some 10 ns range pulses) the amplifiers output is not that low in impedance.
The extra buffer for the BS supply looks like it help reducing the load to OP-amp3, bit I think it makes things a bit worse. With just 1 amplifier the fast part is local to the floating supply.
However parasitic capacitance (e.g. from the logic signals) to ground, can still cause current spikes to the amplifier. So the layout and possible shielding (e.g. with the guard amplfier potential) could have an effect.


Besides the net charge injection and thus the bias current another point is also the size of the charge / voltage pulses visible at the input, especially with relatively little filtering. The smaller the pulse the less filtering / less capacitance may be sufficient. With a good DSO one can likely see the pulse at the input (remove the 10 nF of cause). It may need averaging mode (boxcar integrator mode) to see also small pulses. Getting the pulses small is likely the more tricky part. Ideally small pulses should also cause low net charge injection.

When not using the 10 nF capacitors, but 100 K or 1 M to GND the capacitance at the input may still habe an effect. Chances are it needs a little more filtering there.
For a DMM one usually wants the input offset and bias to be not effected by capacitance (or extra small series impedance) at the input. For this one usually needs some filtering between the switches and the input. The filtering is needed to prevent the switching pulse to get out the input and possibly come back to cause an effect of the charge injection.

The new data with the LV4053 look very good. If the pulse at the input is small enough this would be a good choice (may still need extra testing for low leakage).
It would at least be the simplest solution.

The JFET version is more effort, but possibly less leakage and more options to tweak / trim.

[julian1]

another point is also the size of the charge / voltage pulses visible at the input, especially with relatively little filtering. The smaller the pulse the less filtering / less capacitance may be sufficient. With a good DSO one can likely see the pulse at the input (remove the 10 nF of cause). 

I did look briefly at the input with a scope for the 4053 board.
And then bodged in 100p to gnd, following your suggestion of 20p-200p, in the place of 10M to gnd (R503).

The 100p was removed before starting with the 10n cap tests, since it was 0805 COG and not film, and I was worried about leakage.

In a real implementation, I suppose this cap really needs to be through-hole and PP film

I ordered panasonic 0805 ECH PPS film 100p/50V, but it probably needs testing for leakage. And perhaps higher voltage for ESD/overvoltage events.

--
Edit. Looking at other input filter scheme examples,

3458a    uses RC=5k/82p repeated twice for DCV.
34401a  uses RC=6*1.3k / 470p followed by 2x1.3k/220p.
3457a    uses RC=51k*2/220p for DCV
DVM_input  LC= 1mH/47p * 2

When I get the film cap, I will change the circuit around with better filtering.

[julian1]

Here's a combined schematic with Kleinstein's DVM_input/4053 precharge with DCV ranging, for comment.

Points of interest,

- For 10M impedance and HV divider, Caddock 9.9M/100k 2ppm/C are available (USVD2-B10M-010-02 ).

- Input filtering using two hv through-hole resistors looks neater than a DFM daisy-chain of resistors. Through-hole metal film (RR03J5K1TB)  and PP caps (MKP1839110631) are available at needed voltages.

- For relay choice, agn210 v g6su. agn series are gold plated for better contact at low currents.

- The 1V ref for acal, is only needed temporarily during transfer cal of divider and gain ranges, and doesn't require particularly good (temp,drift) stability. It's not clear if bipolar +-1V is needed for acal.

Pain points,

- 1x/10x,100x gain divider. 34401a, 3458a and Keithley use custom networks.  cern/Reps 8.5 uses custom Vishay v5x5v15x.
      2ppm/C without acal is a good figure to aim for.
      - Caddock 1776-C6815 is 1k/9k/90k can configure as 1k/99k or 10k/90k. but 5ppm/C not 2ppm, and hv is unnecessary.
      - Vishay VTF330SUF  is 1k/9k/90k has datasheet TCR track 2ppm/C. but unknown noise.
      - a total resistance closer to 50k (isntead of 100k) is preferred for 10x gain (and maybe 100x), for lower noise.
      - VSMP foil placed together should be enough.
      - Is there a better solution?

- The DCV filter needs to withstand 1000V when caught on the wrong input range. This is managed with a resistive divider, so that the first filter cap only sees half the excursion voltage. The additional optocoupler switched b2b fets will switch a lot faster than the relay, and help keep voltages and currents manageable quickly. But perhaps a standalone relay switching is enough?

- I am not quite sure about impedance matching the 4053 precharge switch input/output for equal distrubtion of charge injection.  should resistors be placed immediately on each side of the switch? eg. see addition of R518.

- Grounds are hard. i think the main distinction should be between gnds that carry current (resistive-impedance divider/ gain divider), and gnds that have no DC currents (eg. input filtering, mux lo to input amplifier).

- Should the amplifier bootstap be driven with an extra op, for improved CMRR/linearity.

[Andreas]

The additional optocoupler switched b2b fets will switch a lot faster than the relay,

Hello,

I would never put any semiconductors before the RF filter.
(otherwise you may get offsets by rectified RF input signals).

besides this: I do not see how you switch them "ON" without a auxilliary floating voltage referenced to sources of the FETs.

with best regards

Andreas

[Kleinstein]

The FETs driven by an PV optcouplers should be relatively insensitive to RF interference as they are either all the way off or all the way on.
The PV optocouplers provide a floating supply to drive the fets. This is essentially the circuit inside of Photomos relays, just with the parts separated, so that the heat from the LEDs can be a little separate from the signal path and possible thermal EMF effects.

The relay K502 schould not be that critical - it is even optional. The MOSFET stage for the protection can also be used as a switch. K502 would be more to reduce the leakage. Even when off the FETs 503/504 can still have a resistance in the GOhm range.

For the relay K501 one can use 2 contacts in series if needed. This is not so much for the path from the input to the divider, but from the divider to the ACAL signals.

For the first test / proof of pronciple I would consider limiting the voltage a little to get away with simpler / smaller relays. MOSFETs for more than 1000 V also get expensive and sometimes tricky to get.

To keep fast spikes from ESD away from the MOSFET there should be some series inductance (e.g. 100 µH, maybe more) and ideally also some capacitance to ground already before the FETs.
THT resistors for R501 and maybe R502 can make sense - they don't have to be metal film or low noise. The point is only low thermal EMF.  With respect to thermal EMF effects resistos vary a lot and not much data are found, except for good shunt resistors.

Having both a positive and negative signal for ACAL is not much extra effort - the much for the low voltage signals can be a HC4051 or simular. It can help with averaging over 2 points and this way get less effect of the ADCs INL and it gives an extra check in the self test. So I would consider it worth the little extra effort.
Chances are one would need more input paths in MUX. I would consider a 4051 for low voltage signals (+-1 V, +-100 mV, Temperature sensor, optional shunts for current ranges). Another MUX (e.g. DG408 or ADG1208) could be used for less critical signals like the ACAL signal for the divider, buffered signals (e.g. ohm sense L, low current TIA). The sepration to a 2nd / 3 rd mux also has the advantage to allow better isolation from open, unused inputs that would pick up hum.  Depending on how current ranges are implemented there may not be many spare input left.

For the gain setting resistors I would not really consider the Caddock HV arrays. They are quite expensive and may be noisy as they are thick film.
The VTF330 looks good and noise wise should very likely be good or at least good enough.  If really needed to get a lower resistance one could have 2 such arrays in parallel as an option.
The total resistance is a compromose between nonlinearity from self heating and noise. This would mainly effect the 1 V range, though not that much: In the current plan R501 and R502 already give 10 K of resistance that contributes to the noise.

There is one more option for the gain setting resistors: one could use a larger number of equal resistors.  With  10 in series, 1 and 9 in parallel one get a 100:10:1 ratio. 20 equal thin film resistors are not too bad, though the matching is usually not specified, but usually good. The TC specs for the resistors are usually for a quite large range and the performance is the more relevant 20-40 C range is usually quite a lot better. This also applies to the VTF330.

Chances are the 4053 should have about matching capacitors on both the input and output side. One could use somewhat different values to trim / shift the charge injection a little. So there should definitely be footprints, even if one may not be used later. I doubt that R518 would be of any use. If at all a resistor for the C1 input may be useful.

To keep the currents to C503 and the charge injetion at the 4053 local to the floating level, I would prefer to not have an extra OP-amp for the bootstrapped supply. So U501 would directly drive the ground side of the 4053. To reduce the AC current from the control signal on could use a series RC from the 4053 GND to the raw control signal (TP501). R506 should be the same as R509 - probably more 100 K may be 47 K. This way U501 should not see relevant fast current spikes and the charge spikes should stay mainly local.

For the ground the distinction in power ground, signal ground without current and signal ground with current makes sense. Even than one should compensate the ground current if possibly (e.g. for the current from the gain setting resistors).

For the main amplifier the OPA140 may not be good enough with the linearity.  I have not tested the OPA140, but for the slower brother OPA145 I have seen around 1-2 µV of output cross over error when used as a buffer. When used with gain this error would be way to high.  One could reduce this output cross over error in a compound amplifier with a 2nd OP to drive the ouput, though this is a bit tricky with the rather fast OPA140. The other point is the limited CMRR: the specs are only 140 dB typical / 126 dB min and would not guarantee better than 0.1 ppm INL. It may still be Ok as the linear part of the CMRR would not cause an INL error, but just a marginal change in the gain. The problem is that we can't be shure that the OPA140 is linear enough.
When used with a CMOS MUX to switch the gain, the parasitic capacitance to ground can cause stability problems. So one would likely need extra capacitors at the gain setting resistors to compensate.

I have looked at the amplifier circuit used in the 3458.  The advantage there is that bootstrapping the input JFETs is relatively easy (compared to a bootstrapped OP-amp). The extra input stage adds overall DC gain and allows to compensate for more if the linearity errors like the output stage cross over. The part with the inductors at the JFETs is unusual, but it makes sense, at least for a gain of 1 and just boarderline for a gain of 10. It reduces the gain for the highest frequency and this way helps with stabilty (need need for 100 MHz range GBW). However I still don't understand stability with a gain of 100 here the simple analysis show a tendency to oscillation. Maybe the capacitane of the JFETs used for gain switching save the day.

[dobsonr741]

On the mosfet/pv/opto input protection: Kleinstein, what transient behavior are you expecting? Both turn on and off time wise. Is it expected to restrict linearly only to limit the voltage to a max value, or lock and shut down the input completely to zero voltage hitting the ADC? Asking as if an autorange algorithm is working off of the ADC output its better to have full-scale readout when in an underrange position.