Analog frontends for DMMs approaching 8.5 digits - Discussions

[Kleinstein]

Using the differential / driven low side also for a 2nd faster ADC in differential mode is a neat idea. I would not worry about the THD - the OPA140 is quite good in this respect. The accuracy of the extra buffer and intverter would also only effect the common mode suppression, not directly the differential gain.

A possibly issue may be the frequency response: the "inverter" for the low side needs some slow down / reduced bandwidth to something like 1/10 the main amplifier to get overall stability. This is not an issue for the slower DC measurements, but it may be an issue for faster conversions, even if it is only for the common mode part. There would likely be an issue with the input capacitance that is towards the real ground and not the driven low side.
 
One would still need the dividers (like 1:4 or more) for both the low side and main amplifier output to fit the +-2.5 V range for most ADC chips.
One would likely need the divider anyway in one way or the other to also allow for at least a 10 V range with fast readings
Even if the main AC path uses a separate amplifier for better frequency response, it could still make sense to also have a path from the DC amplifier.
This would be more for somewhat faster digitizing, not so much RMS AC. The pure AC path may get away with the native +-2.5 V (5 V differential) range of the usualy ADCs, but may than still need the single sided to differential conversion to use the full range.

[julian1]

OK, I see how to scale to +-2.5V output with a buffered divider -
boot/guard -> divider to driven-lo -> buffer -> inverter.

On the topic of AC measurements, I wonder if there is a modern consensus around techniques for DMMs using COTS parts.

The 3458a direct sampling approach (digitizing) uses the wide bandwidth amplifier, followed by a sample and hold circuit (jfets + teflon cap) with a 2ns aperture.
This feeds the main integrator adc in 16 bit resolution mode.
In 16 bit/4.5 digit mode, the sample rate is 100kHz.
A discrete S/H implementation would likely circle back on low charge-injection switches and precision timing - both topics that the forum has experience with.

Alternatively for modern DMMs,

DMM7510 features AD7982 - 18-Bit, SAR, 1 MSPS ADC, which has an on-chip track-and-hold.
According to the DS, the Aperture Delay VDD = 2.5V = 2 ns
This figure measures,  "the acquisition performance and is the time between the rising edge of the CNV input and when the input signal is held for a conversion."
So *if* this ADC was used for fast AC (and DC) conversions, the 2ns aperture delay is likely relevant to performance and substitutes a discrete S/H circuit.

34470a uses AD9200 10 bit/20Msps. very fast, but much lower bit-depth and dates from 1999.  features a 4ns S/H. and aperture jitter of 2 ps rms.
Perhaps it is just used for rundown.
Also has AD9283. 8-Bit, 50 - 100 MSPS

At any rate, for fast DC or AC digitizing the SAR ADCs look more interesting than the extreme >= 24 bit SD parts.
Also, resistor dividers including for the reference are less critical.

[julian1]

Hmm, I just noticed DMM7510 also has AD637 analog rms converter, so I don't know.

[Kleinstein]

The KS3446x still use the main ADC also for the fast conversions, just with a different input gain. The AD9200 and AD9283 are still only part of the separate build contineous time SD ADC. Chances are the ADC would still reach to around 1 MSPS effective sampling rate to get some 300 KHz of bandwidth. The DMM7510 does not use the fast ADC for RMS, but the DMM6500 does. Also the Fluke 8858 seems to have that.

For the choice of ADC for AC RMS, it depends. With SAR and SD have there pros and cons. With an SAR ADC one could get very high BW, as the RMS BW is limited by the sampling part, not the conversion rate. One may still want some filtering to limit aliasing and noise. Some sort of randomized (actually more like modulated) sampling may help reducing aliasing effects. A digitizing mode may want an aliasing filter that limits the useful BW, likely well below (like 1/5) the nyquist limit.
The relatively fast SD ADCs (e.g. AD4134, AD7175, ADS127L11) can have a well define bandwidth and possibly an adjutable filter / BW. So not as high a BW but less issues with aliasing also for digitzer use.

Higher BW for RMS is not only good, it also makes it more noise sensitive. So ideally one would have BW options, like  1 kHz, 20 kHz, 500 kHz.
The higher frequency AC is anyway effected by the input impedance and the banana plug style terminals are no longer ideal. In quite some cases a modern 12 bit DSO may be the more suitable alternative to a DMM.

[julian1]

The DMM7510 may use AD637 because the design criteria emphasized performance with non-repetitive waveforms.
For AD637 differential mode would not really be needed.

One may still want some filtering to limit aliasing and noise. Some sort of randomized (actually more like modulated) sampling may help reducing aliasing effects. A digitizing mode may want an aliasing filter that limits the useful BW, likely well below (like 1/5) the nyquist limit.

So ideally one would have BW options, like  1 kHz, 20 kHz, 500 kHz.

With an fpga available, a parametized digital FIR / decimation filter would be possible, maybe with a fast mcu too.

Are there any other conditioning steps for the analog input?
The input BW response would be limited by the amplifier (buffer/inverter) and Rf compensation used.
What steps could help randomize/modulate the sampling?
Perhaps multi-channel sampling of the same input but with a staggered/timing offset, and then averaging?

[Kleinstein]

Randomised sampling has the samplig not at a fixed frequency, but more in a somewhat randomized patter. As an example instead of a fixed 10 clock cycles between sample one would have somewhat vaiable times, between maybe 10 and 16 cycles with a pattern that could be some 100 or so samples. As a result the aliasing is spread in spectrum and very unlikely to get a really bad case. I don't know how much effort is needed in looking at the samples when more than just RMS is wanted. It may be tricky to combine randomized sampling with digital filtering. So it would mainly an option if one really wants to include the undersampling frequency range with an SAR ADC.

I don't think the driven low side differential mode makes much sense for an AC front end. I see some issues with the parasitic input capacitance in part to ground and in part to the low side. This complicates the frequency response. One usually wants a relatively simple configuration to have a simple frequency response with not so many adjustment points.

Using the old style AD637 instead of the fast ADC for RMS is more like a missed oportinity based on tradition. So more the traditional old way. When done right, with a little more math the digital method can also work with non repetitive waveforms. It is a bit like having a windowing fuction for FFT.

[julian1]

An extra problem for differential mode is with test voltages/waveforms for ACAL which would need to come from the/an isolated source.
So if a second ADC was included for fast digitizing - then adopting a manufacturer's recommended reference design for a single-ended to differential driver may make sense.
The complexity is not really in the hardware part, and including the necessary footprints could be justified if there is time and board space.

[miro123]

don't understand all the discussions about RMS measurements on bench meters.
An RMS measurement performed by an electrician with 1–3% accuracy and at most two digits is fully understandable.

Going beyond this level requires different hardware and software. It is not an easy task. It’s not simply a matter of putting in a fast sampling ADC and performing some basic math.

For higher RMS accuracy, the industry uses power analyzers like the ones below:

https://dewesoft.com/products/power-analyzers
https://www.hioki.com/euro-en/products/power-meters
https://tmi.yokogawa.com/solutions/products/power-analyzers/wt5000/

Even reading the setup manual of such equipment requires specific technical knowledge. For example:

Are you measuring AC or DC?
Does the AC have a zero-crossing point?
Is the signal symmetrical?
Is the signal repetitive? If yes, what is the repetition interval?
Do you need measurement cycle-by-cycle, integrated cycle-by-cycle, or according to another averaging criterion?
Are you going to use a dPLL for proper phase angle estimation?
How does the DC signal vary in time?

In summary there is huge development in AC measurements, in terms of sofware, compute power and mixed signal HW. It is interesting to observe that HP3458 still remains the benchmark in terms of DC precision accuracy and long term stability whilehist AC capability look like Lego toys nowadays.
In my opinion, every industry leader in this area has its own patent portfolio and pursues its own approach.

If you want to be accurate, you can only measure the RMS value within a well-defined time interval t(t0, t1). All other measurements are based on assumptions, integration, or filtering.

Back to the original question: what does it really mean when a bench multimeter shows 1.23456 V RMS?

[julian1]

I agree AC looks hard, and it may be better to just cut scope.
I think power-analyzers are intended for higher frequency application, while modern DMMs do include AC functions.
If adding a second COTS ADC makes sense to digitize fast DC signals (and keep the main adc simpler), then it seems reasonable to check if it could be adapated for AC.
Particularly if work/effort can be deferred and pushed into software/firmware - because it is acknowledged that it is less important.

[Kleinstein]

Yes, accurate AC measurement open a lot of open points. It is tricky with a normal DMM as shilding and thus more like BNC / triax connectors would be appropriate than the banana type terminals. The shielding part is hardly compatible with higher voltage isolation from ground. At least it gets tricky safty wise.  So I would see accurate AC a thing for a different meter that may than as well do more then just RMS. For a more DC precision meter tt could make some sense to still get an idea of the superimposed AC to detect ripply and similar. This would ideally be separate in parallel to the DC measurements. A digital solution could also check for peak values to get good auto ranging. With the AZ cycle one can not use AC coupling after the main amplifier, as there is the AZ loop modulation. So the AC part may have to start from the input guard buffers (OPA140) with a separate choice of source and amplifier.

An extra problem for differential mode is with test voltages/waveforms for ACAL which would need to come from the/an isolated source.
So if a second ADC was included for fast digitizing - then adopting a manufacturer's recommended reference design for a single-ended to differential driver may make sense.
The complexity is not really in the hardware part, and including the necessary footprints could be justified if there is time and board space.

The differential mode does indeed not work with the simple ACAL sources. Depending on the implemetation it may work for the amps / ohms part, but here it depends and the way with the one stage amplifier as suggested here is not so much compatible.
One can get essentially the same effect by using ACAL sources with both polarities. So have the 10 V / 1 V / 100 mV testvoltages with both polarites and look at the difference from +1 V to -1 V as a 2 V source. One can still also do the step towards 0 and than average over both polarities. comparing both polarities gives a hint on the linearity (the even order components - that the differential mode would suppress).  Already the 3458 has testvoltages for +-10 and +-1 V (though I don't see -100 mV) and I don't know how much is actually used.

[julian1]

The DMM7510, looks like it implements the DC digitizer in a straight-forward way.

A product sheet states - "The digitizing functions employ the same ranges that the DC voltage and current functions use [..] In addition, the voltage digitizing function uses the same DC voltage input impedance (10 GΩ or 10 MΩ) [..]"

So the digitizing function is almost certainly handled by a single-ended to differential conversion on the output of the main amplifier.
And it works as an alternative fast ADC, for non-AZ mode, with the limitation that performance is constrained by the BW of the main amplifier.
(I doubt they have gone to the trouble to add a separate wide-band amplifier, with all the ranging functionality duplicated. And I cannot see another prec resistor divider on the board that would indicate this.)

To get a quick sense of what a minimal implementation of a similar feature might look like, I made a copy of the basics of a ada4941 + ad7982 reference circuit.
Not much effort was put into the symbols, so I would not encourage looking at it too closely, due to the lack of readability.
The parts count is still higher than I would like - so I may not add it - but perhaps others see more value?

There is an interesting example in the ada4941 DS that manages to combine a diff-driver + 100kHz 3 pole sallen key-filter + SAR adc in a simple way.
Unfortunately, no input down-scaling is possible without additional work.

[julian1]

Thinking about it some more -  dmm7510 may well use a fully-differential amplifier, and AZ op-amps through from the front. So no single-ended conversion needed.

[julian1]

The various fast adc approaches all have issues or else are too complicated, so I have dropped this work for now.
In response to the discussions here and in other threads, the current revision includes the following changes, that need to be tested

- input conditioning
  - support driving lo-side (com-lc). for extra ranges - 20V,2V,200mV. following Kleinstein's approach.
  - front-end dithering in both classic and differential modes, using the short-term-stable dac
  - simplify the input fan-in /and ease pcb routing by using a 'feeder' mux (U409) to offload/handle nearby inputs (sense-hi/lo ,hv-div ).

- adc
  - optional input fet modulation, ZGJC, and non inverting slope-gain circuits,
  - the current adc has a probable jitter issue (noise goes up with integration freq), that I suspect is the cmos xtal oscillator.
  but I have also changed the FF from 74lv175 to two 74NN74 footprints, to better support faster logic series FF (74AC), also copying Kleinstein's approach.
  the FF synchronizer and 4053 switch now share supplies, putting more responsibility on the FF for level-shift.

- amps
  - better organization to support differential mode

- schematic
  - attempt to simplify and make more readable.

[miro123]

There is an interesting example in the ada4941 DS that manages to combine a diff-driver + 100kHz 3 pole sallen key-filter + SAR adc in a simple way.
Unfortunately, no input down-scaling is possible without additional work.

What is the sample rate of your circuit? What kind of flatness in the passband do you want to achieve? I assume that you want to achieve 18 bit. It requires enormous flatness.
Which CPU/FPGA is used to digest sampling data?

[Kleinstein]

Jitter is a noise source at the ADC. Besides jitter there is also the switch capacitance that is connected / discoonected from the integrator to add some noise, that behaves similar to jitter (though it does not scale with the reference voltage).
So a little more noise with faster modulation is normal. It is only a question of how much.
With the rather low DA capacitors there is no longer the need to go as high in the frequency as the 3458 or 34401 (more for resolution reasons, not DA) do. I currently get away with some 57 kHz modulation and still have an DA related INL of less than 0.1 ppm FS (without dithering).
There are quite some modern cheap oscillators with jitter specs of around 1 ps_RMS, which should be good enough and comparable to the jitter from 74AC or the LV4053 switches.
Faster modulation reduces the INL from DA, but it makes switching related INL (e.g. integrator settling, supply transisents) more important.

If needed, one could consider a 2nd order integrator for the run-up and this way hopefully reduce the error from DA addionally. The run-up would used the 2nd order path, while the run-down would still use the 1st. order only. This way a slower modulation frequency would get viable.

With the switch supply voltage modulation (to compensate for nonlinear R_on) I would only modulation the switch voltage, not the FF voltage. The change in the voltage is anyway small ( 20 ohm * 0.3 mA = 6 mV)  and there should be no issue with the FF voltage staying constant.

With the ADC it is not a good idea to share the same dul OP-amp for the precision OP in the integrator (U908A) with the ground buffer. The Precsion part should be a single OP-amp with separate decoupling as it is the critical part.
It would be good to have the fast part of the integrator (U909A) share a dual with the ground buffer. The ref. current is switched between these 2 opamp outputs.

The Zjump part (as coppied from the 3458) would not need a super faster comparator. The latch function that slow comparators usually miss could be part of the FPGA. This way the control would also know the setting.

For the reference amplification it can really help to have some low pass filtering at the ref. input. This would a resistor in the ref-hi path and a capacitor to ground or to ref-n14V  (gives addtional gain to the capacitor). I have some 6.8 µF there and removing this capacitor nearly doubled the ADC noise (though with a more noisy LM399 ref.).

There is no need to short out the current input for ACAL. If it all one may want a shortening realy for the current input, so that the current could still flow when isolated from the measurement path.
I don't think it is a good idea to have the relay to disconnection the overcurrent protection. It would be more suitable to inject the ACAL test current to a later stage instead. The 1 K shunt would not want a very high voltage anyway.

The TIA part would be tricky for the very low currents: the switch leakage causes problems and also leakage from the input protection would be an issue. The TIA is nice for small currents like a 10 µA or 1 µA range, but not much below. The question is a bit if it is woth the trouble with switching ranges.
For the really low currents (like 1 µA FS) one would not need / want an AZ amplifier at the TIA. Here the OPA140 / OPA145 would be good. The limiting factor is here more leakage and input bias.
For higher currents (e.g. 10 µA , 100 µA) an AZ amplifier could make sense, but would need to compromise with bias and current noise.
With the higher voltage at the TIA one no longer really needs 1:10 resistor steps. Also 1:100 steps can be good enough.
Instead for resistor switching at the TIA I would consider 2 separete TIAs for high (e.g. up to 100 µA)  / low currents (e.g. 1 µA or 3 µA).
The current part may want a bit more makeover. A point I am missing is a suitable shunt to use as the reference for ACAL. the 900 ohms are a bit on the low side and 1 M at the TIA is too high.

[julian1]

What is the sample rate of your circuit? What kind of flatness in the passband do you want to achieve? I assume that you want to achieve 18 bit. It requires enormous flatness.
Which CPU/FPGA is used to digest sampling data?

Yes, this is probably why the 3458a uses an independent wide-band amplifier that is optimized for the task of digitzing (for AC).
Also, as Kleinstein notes, it is not particularly compatible with heavy input protection, and the various capacitances to the enclosure, and guards,  input muxes etc.  (fast DC probably tends to the same problems as AC)
For a brief moment, it looked like all that was needed was to take an off-the-shelf part and put it on the pcb, but I have stopped looking at it now.
It is still educational to discuss it, and identify the issues.

Jitter is a noise source at the ADC. Besides jitter there is also the switch capacitance that is connected / discoonected from the integrator to add some noise, that behaves similar to jitter (though it does not scale with the reference voltage).
So a little more noise with faster modulation is normal. It is only a question of how much.
With the rather low DA capacitors there is no longer the need to go as high in the frequency as the 3458 or 34401 (more for resolution reasons, not DA) do. I currently get away with some 57 kHz modulation and still have an DA related INL of less than 0.1 ppm FS (without dithering).
There are quite some modern cheap oscillators with jitter specs of around 1 ps_RMS, which should be good enough and comparable to the jitter from 74AC or the LV4053 switches.
Faster modulation reduces the INL from DA, but it makes switching related INL (e.g. integrator settling, supply transisents) more important.

From memory, I had to go down to around 20kHz to get reasonable (3458a comparable) noise.
INL was OK, but I didn't do too many tests, since I wanted to wait until it could be fully automated.

I never looked at jitter specs when selecting a cmos oscillator, and just assumed any part was likely good enough.
Subsequently I purchased some better parts with a jitter spec to test.
The pcb footprint can now accommodate basically any standard pinout part in different sizes.

 
If needed, one could consider a 2nd order integrator for the run-up and this way hopefully reduce the error from DA addionally. The run-up would used the 2nd order path, while the run-down would still use the 1st. order only. This way a slower modulation frequency would get viable.

Thanks for explaining this.
A 2nd order integrator, is a cascaded integrator.
So one steers the RU based on the output of the second/following integrator - in order to keep the average charge on the capacitor of the first integrator closer to zero (which reduces DA)?.
while RD works the same.
My preference is to follow traditional practice/design - at least before getting things working end-to-end.
But if if the second integrator only needs a low-spec op-amp/ resistor/ cap and comparator, and can be made optional, it becomes more interesting,
pcb space may be a limitation.

With the switch supply voltage modulation (to compensate for nonlinear R_on) I would only modulation the switch voltage, not the FF voltage. The change in the voltage is anyway small ( 20 ohm * 0.3 mA = 6 mV)  and there should be no issue with the FF voltage staying constant.

With the ADC it is not a good idea to share the same dul OP-amp for the precision OP in the integrator (U908A) with the ground buffer. The Precsion part should be a single OP-amp with separate decoupling as it is the critical part.
It would be good to have the fast part of the integrator (U909A) share a dual with the ground buffer. The ref. current is switched between these 2 opamp outputs.

OK. that makes sense.

The Zjump part (as coppied from the 3458) would not need a super faster comparator. The latch function that slow comparators usually miss could be part of the FPGA. This way the control would also know the setting.

That was my initial thinking that I discussed - just use a lm311 or lm1871 (ie. with gnd-referenced/level-shift output), and have the fpga manage the logic.
A nice advantage is that the function can be turned on/off without adding/removing parts.

But without hysteresis, a pathological input voltage could cause the comparator to self-oscillate
This does not matter for the logical function of the sample/latch - any value will do, it just needs to be held constant across the duration of the readings.
But it could produce EMI that propagates on the output - and power supplies.

By contrast - for a comparator with an integrated latch, the oscillation would be limited inside the part.
And in the best-case the latch function would disable the internal current-sources to the comparator front-end and avoid internal oscillation.
So copying the 3458a circuit looked like a simple way, but using a part with lower power consumption (lt1671 instead of lt1016/to3016).

An alterantive approach would add positive hysteresis, but this would carry hardware state across readings.
But perhaps a fet switch to short a small bias in the gnd input would work better.

For the reference amplification it can really help to have some low pass filtering at the ref. input. This would a resistor in the ref-hi path and a capacitor to ground or to ref-n14V  (gives addtional gain to the capacitor). I have some 6.8 µF there and removing this capacitor nearly doubled the ADC noise (though with a more noisy LM399 ref.).

Did you use a PP film cap?
I carried a MLCC cap through multiple schematic revisions, but removed it because I felt a non C0G type would not be good enough.
With the reference factored out into a daughter board - there is more space to mount a large film cap.
But then the filter would apply to all uses of the reference (ie. acal) - not just to create the adc ref-currents.
But perhaps that is OK - all uses of ref-hi are buffered.

There is no need to short out the current input for ACAL. If it all one may want a shortening realy for the current input, so that the current could still flow when isolated from the measurement path.

OK. this makes sense.
Probably it would be good to introduce the short, when ranging and relay contacts are momentarily open.

I don't think it is a good idea to have the relay to disconnection the overcurrent protection. It would be more suitable to inject the ACAL test current to a later stage instead. The 1 K shunt would not want a very high voltage anyway.

For amps, I moved the ACAL test current injection point to before K701.
This allows the large protection lifting relay to be removed - which is 1000% better.
And the first relay is now a simple shorting relay.
Also added a higher-val shunt for acal.

[Kleinstein]

The reference filter capacitor can be a film type. I have even just a mylar type, so not even the higher grade PP type. The filter sees an essentially constant voltage. The DA loss causes a little extra settling time, but this would be only some 10-100 seconds following turn on.

The extra integrator for 2nd order integration should be OK with a low grade OP-amp (like MCP6006 or a little faster). Noise of this OP-amp would only add some additional dithering to the run-up. I have still not tested the idea and don't know the requited capacitor size (likely in the 10-100 nF range).

[MiDi]

3458A heavily relies on AZ, even with AZ off, the first reading is with AZ.
The ZGJC adds an offset of around ±200mV depending on the input voltage, so that the ADC only sees voltages higher than +200mV or lower than -200mV.
The offset is simply removed by the AZ action, as the zero reading always has the same offset voltage applied as the input reading.
Downside is additional degraded drift w/o AZ originating from R185 & R184 tracking to U180 RN - but might not be that relevant as there are other parts contributing: R182 (|| R183), R122 (A1) and the AFE.

[julian1]

The extra integrator for 2nd order integration should be OK with a low grade OP-amp (like MCP6006 or a little faster). Noise of this OP-amp would only add some additional dithering to the run-up.

Why a single-supply/rrio instead of a bipolar op-amp for the second integrator?
If you input bias at VDD/2, the output of the first integrator would need to be level shifted.
Or is the goal to intentionally shift the first integrator output average value slightly away from 0V to reduce DA?

[Kleinstein]

For me the idea with a RR OP-amp for the 2nd integrator is using a µC internal comparator input. For this it gets easier if the OP-amp has the same supply as the µC. With an inverting integrator, there is no need for level shifting and the comparator trigger level can be at half the supply.
With an external comparator one could of cause use a higher supply OP-amp.
It could still make sense to have the OP-amp (e.g. OPA171) with only a positive supply, so that the comparator (like LM393, TLV1701) can get away without level shift at the output.

[Kleinstein]

Here is my version for the suggested driven low side part. The idea is to drive the low side opposite the high side to double the input range, especially in AZ mode. To help with INL tests based on the sum of 2 voltages it would make sense to have 2 low side terminals and maybe also a 2nd high side. The 2nd high side can also be used as part of 4 wire ohms.

The driven low side is combined with a DAC, that can be used as an auxiliary output for measurements relative to ground and for extended self tests.
At max setting a multiplying current output DAC acts as an inverter. So the DAC part can also be used as the inverter via the same output path.

The suggested relatively simple configuration has first an 1:8 MUX (e.g. DG408, ADG1208) for the DAC reference. The choice is +-10 V, +-1 V from a divider from the ADC's +-14 V and the guard signals from the inputs. The 2 remaining inputs could be 100 mV, the 7 V ref. level or GND, but would be free for changes.
A buffer (e.g. OPA207) than drives the DAC ref. . The DAC output can provide the test voltages for the ACAL part.

The low side inputs have protection with back to back MOSFETs, a PV-OK for the gate drive and 2 BJTs for a current limit at some 1 mA. So similar to the main input, but probably without the extra opto-coupler for a fast off. Both low sides get a path to the main amplifier input. This is to read the low side in differential mode and also to use the low side input as low grade (more leakage and no pre-charge) inputs, e.g. as ohms sense low.

For the first low side a MUX like ADG1208 could choose between multiple drive signals. This are a direct link to ground, the DAC output, an extra driver OP-amp output for the DAC with Fb either local or via a separate input (e.g. 2nd low side), the DAC with an 1:1000 divider (for DNL tests). Other possible signals would be the DAC ref. level, an input guard signal (use as driven guard) and also internal test signals like a supply with divider or a temperature sensor. It would also be possible to have a low current TIA (e.g. 1 M FB resistor).

The 2nd low side could be a bit simpler with only 2 drive signals (GND and the DAC) that could be switched via 2/4 of a DG413. The other half of the DG413 could do the FB switching for the driver part.

Attached is an overall overview and a rough plan of the low side switching part with DAC.

[julian1]

Using the mdac directly as the inverter (instead of as an output to a fixed divider inverter) is really nice.
With R44/R82. 100k/100R. a classic input + small offset comes for free, with reasonably low impedance - and with the full 12bit mdac scale.
Alternatively just writing a low value to the mdac register would also work with less resolution.
It helps that the TI mdac supports +-15V for the ref pin, unlike the AD part that goes +-10V.

I think I can see that the constant +-10V input (derived from ref14V) could be used as fixed ref/steps, to make constructing a multi-part sum test to cover the full 20V input range possible.
Perhaps that is also why ref (without being inverted) can also be be muxed directly (from u20 to p4,u9) .

The DG413/U16 uses complementary switch logic, but I am not sure what the intention is or why it is used for muxing the output of LS2.

[Kleinstein]

The 2nd low side LS2 is a simpler version as one usually does not need all the extras on 2 terminals. One could as well use another 1:8 or 1:4 mux, but it would be more effort.
The complementary DG413 (alternatively DG213) is used to use it as a SPDT for the driver feedback. It also allows an easy interlock with the diode and resistor to prevent both switches on.

Having V_ref without the DAC as an output option can have 3 uses: one is getting V_ref from Guard1 or Gurad2 and than have the LS1 as a driven guard for that input. The other is to have V_ref at LS1 and the DAC at LS2 to have an external voltage up to 20 V. Finally without the DAC the output can be a little more stable. This would especially help if the free ref. input would be the raw 7 V reference.

In the protection I have FETs for some 1000 V.  For use between a LS and high side therminal the 2 protection parts are effectively in series. The LS protection works as a 2nd line of defense. This however does not work with a voltage relative to ground or the amps part. So less protection for that use case.

The 12V limit with quite some of the AD DACs is anoying. AD still has a few that can also take 15 V  (e.g. AD5553). The higher resolution tend to have 5 K ref. input resistance and may thus show thermal effects.

[julian1]

Using bjts+fets as current-limit (1mA) for LS protection is nice, because it avoids the need to add an extra buffer op-amp to bootstrap the protection diode/tvs.
This works because the LS is often driven/low-impedance anyway (using mdac out, gnda), so no guard needed even for pcb leakage.

But a LS current-limit protection approach will also limit the current through the BJT optocoupler that shorts the gates of the HS protection series fets -  and reduce their effectiveness.
This would be the case for external over-voltages where high-side and lo-side are in series with GND as common.
An over-voltage event between LS1,LS2 (eg. 4W LO, and COM) is OK.

But perhaps the correct conclusion to draw here, would be to just remove the fet-shorting bjt optocoupler from the HS protection as well.
So the HS protection would rely on the current-limit (bjt+fets) as well as the bootstrapped diode/TVS to gnd.

[Kleinstein]

The extra optocoupler at the high side is to shorten the gate - source voltage. This allows to reduce the current in case of an overload. I have this with my current DMM and it works well. AFAIR with overload the input current is limited to some 20 µA , that is just enough that the optocoupler can short out the current from the PV coupler. The BJTs at the high side are more as a backup for fast transients - not sure if they are needed at all.

The low side has additionals switches and this way more leakage current anyway. One could still have the extra buffers to bootstrap the protection. One could at least use cheaper parts (e.g. TL032 or TLV9302) and depending on the TVS leakage leave them out.
If used as inputs the LS terminals are of lower grade without pre-charge (thus AZ mode switching spikes) and maybe leakage in the 100 pA range. This should still be good enough for something like Ohms sense low and less demanding signals (e.g. voltage references).

There is no issue with an overvoltage between a low side and a high side. Up to some 800 to 1000 V the high side protection would work similar to the case with a voltage to ground with a current in the 20 µA range. When the spark gap/MOV or MOSFET avalange limit is reached the low side current limit (some 1 mA) would activate and could absorb up to some 800 V or so, limited by the FETs or an optional MOV.
One has a slight problem in using the active low sides as the ohms drive terminal for higher test currents. So a 20 ohms range could not use the LS1,LS2 terminals. For high resistance the active low side would be interesting as they would allow a higher voltage, e.g. for a 20 M or 100 M range.