R1 needs to be trimmed for a low TC. I have not checked the numbers very accurate, but expect some 1-10ppm/K of TC for 1% deviation of the value. The initial trim part, down to some 50 ppm/K is relatively easy, the fine tuning can take quite some time, as one than starts to get the square part of the temperature dependence too. So one needs to wait for the JFET too cool down - not to get a low TC at the wrong temperature. It really helps to have a good DMM (e.g. 6 digits, ideally with a graph) for the adjustment, ideally also a temperature sensor at the reference.
The final voltage setting with R5 and R6 should not effect the TC very much.
The voltage can vary quite a bit (e.g. some 4 - 9.5 V for the 2N4391). So the value for R1 can also vary quite a bit (even a little more, as low voltage FETs also tend to like more current). So one may want to first do a test with lower grade resistors and check for noise and only than order the final resistors, with still a little room for a fine tune.
I did a quick test with a J111 (essentially the TO92 case version of the 2N4391): it kind of works OK on the bread board and the low frequency noise looks promising, e.g slightly better than LM329.