Building your own voltage reference - the JVR

[TERRA Operative]

What's the significance of the asterisks alongside R1, R5 and R6?

[exe]

What's the significance of the asterisks alongside R1, R5 and R6?

These resistors need to be adjusted. R1 needs to be trimmed for zero tempco, R5 and R6 define voltage gain. We need to adjust gain because voltage reference J1 has loose tolerance.

I'd myself wouldn't try to trim all three resistors and once. I'd first figured out the value of R1, and supplied J1 with the desired final output voltage (what we expect to have at U2 out, typically 10V). After adjustment of R1 is done, I'd trim R5 and R6 (I think only one of them needs to be trimmed) so that final output matches what we expect.

[Kleinstein]

R1 needs to be trimmed for a low TC. I have not checked the numbers very accurate, but expect some 1-10ppm/K of TC for 1% deviation of the value. The initial trim part, down to some 50 ppm/K is relatively easy, the fine tuning can take quite some time, as one than starts to get the square part of the temperature dependence too. So one needs to wait for the JFET too cool down - not to get a low TC at the wrong temperature.  It really helps to have a good DMM (e.g. 6 digits, ideally with a graph) for the adjustment, ideally also a temperature sensor at the reference.

The final voltage setting with R5 and R6 should not effect the TC very much.

The voltage can vary quite a bit (e.g. some 4 - 9.5 V for the 2N4391). So the value for R1 can also vary quite a bit (even a little more, as low voltage FETs also tend to like more current). So one may want to first do a test with lower grade resistors and check for noise and only than order the final resistors, with still a little room for a fine tune.

I did a quick test with a J111 (essentially the TO92 case version of the 2N4391): it kind of works OK on the bread board and the low frequency noise looks promising, e.g slightly better than LM329.

[dietert1]

I checked ten J105 parts left from a previous repair and found pinch-off voltages between 6.8 and 7.5 V at 10 V input. This was at about 1 uA source current (DVM input impedance = 10 MOhm). Then i used two different source resistors 4K7 and 4K7+6K8=11K5 to measure output impedance to be between 84 and 113 Ohm. Source resistor attenuation would be 60- to 80-fold.

With one of the FETs the pinch-off voltage was 7.35 V. Tried to find a low TC point starting with 4K7 as source resistor and stopped after trying various values down to 1.3 KOhm, always with strong positive TC. In the end the FET had more than 5 mA of source current and was operating well below the recommended gate voltage = pinch-off - 0.65 V.

Then i tried TC compensation with a thermistor in the source circuit. I used two 4K7 MF resistors in series and the 10K thermistor parallel to one of them. Now source current and TC are both small. Output voltage is 6.905 V - similar to a TC compensated zener reference. Next step would be fine tuning in the oven, but before that i will get and try a TO18 2N4391 as recommended above.

Regards, Dieter

[dietert1]

Meanwhile i got 10x 2N4391 and found a pair of them that gives 10.041 V at 1 mA when stacked upon each other. That appears to work very well and is much easier than finding a 2N4391 with 10 V pinch off voltage. The maximum i found was 7.1 V and it dropped to 6.3 V at 1 mA. So better combine two of them.

I think this is a way to make an excellent metrology reference:

- TC of this 10 V reference is positive and about 12 times less than the usual 6.2 V zener, so you don't compensate 300 ppm/K but 25 ppm/K down to a fraction of a ppm/K. A very similar compensation scheme can be used: based on a fraction of a pn junction CTAT.

- Noise is also expected to be lower (no zener noise, no gain stage with voltage divider).

- In a divider from 10.041 to 10 V we only need precision for 41 mV. No problem with TC of some ppm, it will be attenuated a factor 200.

- If you think about the long term stability of wire bonds the small current through the reference appears an advantage.

Regards, Dieter

[Kleinstein]

For trimming the TC, the obvious way is to trim the current. With the right resistance value the linear TC can be trimmed to near zero - a little like it was done with the old 1N829 compensated Zeners.  It is not very convenient for mass production, but for a single unit as a hobby project this is very feasible. One should get below 5 ppm/K without too much effort.

Ideally one would have some kind of simple oven and temperature reading, to aid in the adjustment, especially at the fine end.
A simple oven regulation would also be effective against the higher order TC and with a well trimmed linear TC the demand on the oven is no longer that high.

A difficulty is the large scattering in the voltages.  Chances are a batch of fets would be relatively close - so one may not have much to choose from and ordering 10 or 20 pieces from a single source would not extend the voltage range a lot.  Getting 2 FETs to give close to 10 V is more like a lucky find - I would not count on this.

As far as the data-sheets tell, the zero TC current would change a little with voltage. So stacking 2 FETs with significant different voltage would likely result in slightly positive TC for one fet and a slightly negative TC for the other. So temperature differences could cause an error. A resistor in parallel to the lower FET (with higher threshold) could compensate, but is extra effort.

[dietert1]

The reason why i am not using current to compensate TC is in one of your previous posts: The difficulty to adjust, since the source resistor should be a precision resistor. In my test setup i am using a 5K UPW50 that we had. The lower JFET gives 5.46 V of which i am using 0.55 V for the diode, so i get almost exactly 1 mA. Parallel to the diode i have a voltage divider to drive the lower FET gate with the small compensation signal. I think that divider can be made with standard MF resistors.

To keep temperature differences between the two FETs and the diode as small as possible, i soldered them one next to each other into a small raster board. Thermal coupling can be improved by potting that part of the board and finally using an aluminum enclosure as oven. Or use plastic FETs that can be glued into a common piece of copper.

Concerning the "lucky find" objection: Of the ten JFETs i had two got destroyed during experimentation (pinout confusion). From the remaining eight i found that pair with 10.041 V, but there are 3 pairs between 10 and 10.3 V. Statistics helps if you start with 100 parts.

Regards, Dieter

[Kleinstein]

Using a diode in series with the resistor will change the TC, even if not tapping of a part of the diode. It should shift the zero TC current more towards a lower current.  In addition it would effect the 2nd order temperature effect , though I don't know if it would make things better or worse.
For adjusting the resistor, there is still the option to combine a precision resistor with an smaller series one or larger parallel one. If the good resistor is not too far off, the additional resistor would be not as critical. Not sure if the combination with a diode and resistors for a trim is more stable. It probably depends on how good the initial guess is.

When starting with a bag of JFETs near 5 V it is easy to find a pair for 10 V. However it is well possible to have bag of 100 FETs all higher than 6 V. Variations inside a batch can be limited. Still even with 2 x 6 V = 12 V or with some 7.5 V from one Fet one would have a better start for a transfer to 10 V than from the usual 6.9-7.2 V.  7 V is about as bad as it can be:  2 in series and a divider down is about as bad as the direct amplification. So every thing away from 7 V would be an improvement for scaling to 10 V.

[dietert1]

An incubator test 20 °C to 40°C to see whether the diode compensation signal is linear was done before, but that was using a single JFET and a HP 3478A meter. In that test  deviations from linear were within resolution = 20 ppm, with no indication of a nonlinear term. From that test i learned that for perfect compensation one has to take into account the source follower gain which is slightly less than one.

Will repeat that with a more complete circuit including reference buffer and 10 V to 15 V gain stage as intermediate supply. And with more precision to look at ppms and below. Maybe using 14 V as intermediate supply it can work with the 15 V supplies we have.

Regards, Dieter

PS: The 2N4391 are Motorola NOS and i already ordered another batch from somewhere else.

[Kleinstein]

I did a quite test for the temperature dependence with an 2N4391.  In my case the voltage is at around 6.8 V - so kind of comparable with the classical 7 V ref.  I currently have a combination of simple resistors, but heating the JFET only. As a funtion of temperature the voltage shows a maximum.
Having a diode as part of the source resistor would increse the current with higher temperature this would cause a more downward slope. So the diode would increase the 2nd order effect.

The split in the up/down part is likely due to not so good thermal coupling to the sensor (diode).

[dietert1]

Today arrived  another batch of 10x 2N4391 (mixed Motorola and Philips) and now i got six pairs with 10.024 V, 10.041 V, 10.041 V, 10.054 V, 10.088 V and 10.195 V, a nice result. For both batches i spent about as much money as one LTZ1000ACH - plus several hours of characterization and selection. Until now a bit of try and error.

Kleinstein, i observed that 2N4391 source voltage TC at  1mA and room temperature is positive and lower for higher pinch-off voltage parts. The part you are using probably has a pinch-off of about 7.6 V. The test i mentioned above was with a 2N4391 at 1 mA and 5.5 V Ugs. It showed positive TC up to 40 °C .

Regards, Dieter

[Kleinstein]

One gets a positive TC with a resistor that is larger than optimal. I get about 15 µV/K more for another 100 Ohms extra. So to get the TC down to 1 ppm/K one would need to adjust the resistor to some 50 Ohms.

The Drain voltage has quite some effect on the voltage and suitable resistor. So it absolutely makes sense to get this from the amplified ref voltage. If this voltage is only used for the supply, one could do the fine trim of the TC also here, at least for a small range. To avoid extra 1/f noise one usually wants a relatively low drain- source voltage (e.g. < 5 V).

The 2nd order TC at some -0.19 ppm/K² seems to be comparable to what one gets with compensated zeners. So for a really stable reference one would need either a stable temperature or a compensation for the 2nd order effect.

[dietert1]

In a first determination of curvature for one of the JFET pairs i also got a flat max of the temperature curve, with -0.054 ppm/K² curvature. Since i compensate the linear term, the max temperature is in the middle of the temperature sweep (20 °C .. 40 °C). You can also see that this time i need 0,36 of the diode correction signal.
Next i need to improve and automate my setup to look at it below ppm level.

Regards, Dieter

[SilverSolder]

I have a question on temperature correction:   Is the temperature dependence repeatable? - e.g. so if you know the temperature, you also know the offset?

I'm thinking, you could measure the specific device and create a lookup table in a small micro that compensates the reference (either mathematically after the fact, or via a D/A converter feedback to the output voltage).  Workable?

[Kleinstein]

The temperature dependece is rather repeatable. The slope depends on the current / resistor used , but for give device it should be rather stable.
A feedback from a DA may be possible. It may still be good idea to first adjust the lineat TC to a low value (e.g. bring the temperature of the maximum to something like 10 - 40 C), so that the deviation range is small and thus not too much correction term. To keep the low noise level I would expect that DA steps would have to be a little below 100 nV - so some 10-11 Bit to corret up too 100 µV.

The alternaive would be a temerature regulation to a litte above normal operating temperature. With a well trimmed linear TC the redulation would not have to be so accurate.

[Cerebus]

I have a question on temperature correction:   Is the temperature dependence repeatable? - e.g. so if you know the temperature, you also know the offset?

I'm thinking, you could measure the specific device and create a lookup table in a small micro that compensates the reference (either mathematically after the fact, or via a D/A converter feedback to the output voltage).  Workable?

Reasonably predictable. The temperature dependence curve is subject to hysteresis, so you have to know the temperature history, it isn't just a straight temperature lookup. The amount of hysteresis is also dependent on how far out the temperature has wandered. So, it isn't simple. The more history you have, the better a temperature dependence model you can build, but it's a model you need, not just a simple lookup table.

[dietert1]

We have two LTFLU references that run in hermetic TEC ovens at about 17.4 °C and 27.7 °C and i can tell that no significant shifts (more than  0.03 ppm) have been observed after temperature cycles. Those were accidental oven shutdowns or during reconfiguration. I'd suspect that temperature hysteresis is more relevant for high temperature ovens like the LM399 or the LTZ1000, but not at lower temperature. As far as i know most of the experts here do not implement the Pickering anti-hysteris cycling in their LTZ1000 references.

Regards, Dieter

[Kleinstein]

Hystersis is more a thing of larger excursions, much less of small excursions. The absolute temperature would not make that much of a difference - this more like changes the time scale for thermally activated effects.

 When the temperature is set relatively close to room temperature there are usually no large excursions. The ref. chips are build to have low hysteris - we don't yet know how bad it is with the JFETs that are not specially made to have low hysteresis.

I did see a little hysteresis, but not much and this could very well be from the not so ideally places temperature sensor and from contacts (I still have the FET in a socket).

[dietert1]

No, you didn't see hysteresis. You don't know what you saw.

Regards, Dieter

[Kleinstein]

I did a quick test on the noise levl of the JRV refernce. As the noise is relatively low, this is not so easy.
The main idea is to build kind of 2 JRV type reference (2N4391 + 6.18K + stable drain voltage) and measure the amplified difference.

For the amplification one of the references is modified, so that the gate is used for feedback. So the circuit is the same as the old days combination of 2 JFETs as source follower before an BJT based OP.
The drain voltge is stabilized from the 1st unmodified ref. part.

Attached is the first test, so there is still quite some temperature rise with time - which is kind of positive.
The resistors are such that the idividual temperature drift is relativly small, though not perfectly. For the differnce one has a temperature dirft of some 20 µV/K - so not good for an amplifier, but not so bad for a crude hacked togetger reference at some 7.1 V.

The curve shows the change in voltage difference over some 12 minutes plotted versus a diode voltage to measure the temperature change. The temperature rise is still relatively linear in time.

The noise is surprisingly low with some slight signs of pop-corn like jumps.  Some of the noise may still be from the crude setup and simple resistors (may still be thick film, though not sure).  So there is a chance to get a really low noise refernce.


edit: add circuit diagram for the test

[Kleinstein]

I just realized the drain voltgate part was not really working - so some of the noise / drift could be from that end.
I repeated the part with working drain voltage part and changing the amplier OP to an OP27  (much of the higher frequency noise was from the OP07 - and the OP27 still conributes).
The plot is this time versus time and not "temperature" and a little more zoomed in.

So it looks like the  10 seconds peap to peak noise can reach the 1 µV region - so about comparable with LTZ1000 / LTFLU.

[exe]

Kleinstein, on your schematic both Q1 and Q2 have same source resistor. It means that at least one of them not trimmed for zero tempco. So, can be part of change in voltage difference is due to temperature change?

[Kleinstein]

The tempco is not trimmed very well, but the residual TC for the difference is also not so large (20 µV/K range).  For 1 of the JETs the TC is reasonable well trimmed. The general slope in the plot versus temperature is very likely the temperature effect. The noise may be a littel better with better adjusted resistors, but I would not expect that much improvement.

The noise part is more like small jumps of some 0.5 µV - this is definitely not a temperature effect.  The short time noise bewteen the jumps has parts from the OP, especially in the first curve.
The points are 20 ms integration and thus 25 Hz noise BW. The data are 1 point about every 81 ms. The "missing" points are not expect to contribute much to the noise. So the data from 10s windows should about reflect the 0.1 Hz to some 10 Hz noise.  The exact upper end of the frequency band does not make much of a difference in this case, as there is little noise between some 5 and 25 Hz.   

[dietert1]

Meanwhile i automated my dual JFET reference setup.  I am using 2x Fluke 8502A (A and B). To check for hysteresis i tested temperature dependence at various fixed temperatures - no scan because of sensor lag. This test shows no indication of hysteresis above a limit of maybe 0.5 ppm. Only the first point at about 20 °C shows more deviation, but i know that the DVMs drift a little in the morning while warming up after the night.
This time the diode voltage is a bit higher, since i omitted the 1K resistor parallel to the diode (placeholder for TC divider). I was hoping that curvature would reduce. But results are the same as before (-0.060 ppm/K²).

Regards, Dieter

[Kleinstein]

If I understand it right, a diode in series with the source resistor would add to the curvatutre, though not very much. With increasing temperature the current for the reference could go up, and a high current gives a more negative TC. So the curvature gets larger.

A diode at the drain side could help a little to reduce the curvature: lower drain voltage reduces the reference voltage and current. The ideal zero TC current would also drop a little, but not as much. So one could get a little compensation for the curvature. However from my estimates the effect would be rather small. So I don't think it would be practical to fully compensate the curvature this way. With the 2 JFET version the diodes could be between the FETs: the DS voltage should ideally not be very large (e.g  > 5 V) anyway.