Design considerations for 8.5 digit front end

[sahko123]

Context: I am designing an 8.5 digit ADC with surrounding voltmeter with a novel self-calibration technique as part of my final year project. (about which i will share but not until the project is finished).

As part of the ADC I need an input buffer and believe an ADA4625-1 unity gain buffer should be sufficient. Mostly because this is more about the ADC and getting a +-10V voltage digitized as accurately and precisely as possible. The following project would be about getting other functions such as I and R along with various voltage ranges but for now the ADC is the priority.

does anyone have any suggestions on the input buffer or should it be more than enough for the project at the moment?  Is there anything Im missing? or should this suffice?

[coppice]

Lets says 8.5 digit means a maximum count of +-200,000,000. The step size for 10V would be 50nV. An ADA4625-1 seems to have a offset voltage spec of 80uV typical. Does that seem suitable? Even if you are frequently self calibrating away that offset, just how well temperature controlled would the op-amp need to be tame its offset voltage drift to 50nV between calibrations?

[sahko123]

The offset voltage of 80uV I should be perfectly fine. but the tempco can possibly be better. The typical is actually +-0.2uV/C with a maximum of 1.2uV/c

[iMo]

FYI - not targeting 8.5digits, but an attempt to find a simplest way to create an AFE for the high-end single chip ADCs.

https://www.eevblog.com/forum/projects/simple-dc-afe-for-adc-chips-with-unipolar-diff-inputs/msg2120179/#msg2120179

[Kleinstein]

The offset (and drift) is one of the lesser problems if the front end does some kind of auto zero by switching between different inputs, including a 0 V (or similar).  The CMRR could be a liniting factor for the linearity.  With typ. 130 dB this not enough to guarantee better than 0.3 ppm INL. However chances are that much of the CMRR is still linear - so from this side it can be just acceptable, though not great, when hunting for possible sources of INL.
Another important parameter is theg gain, as this effects how good the OP-amp can compensate for internal nonlinearity, especially the output cross over. Here the ADA4625 is quite good - though the cross over error could still be a point to whatch for. With the OPA145 I was able to see that type off error. Adding a constant current load can avoid the cross over error by operating the output in a class A range.

For a buffer it is relatively simple to use a bootstrapped supply and this way essentially eliminate the effect of the CMRR.

An alternative buffer would be a Zero drift OP-amp like LTC2057 or OPA189. These usually have very good CMRR and gain, at lest for DC and low frequencies.

[miro123]

1. What are the input parameter/requirements -  e.g. BW, input R and Z
2. What are parameters of of ADC input - e.g. does ADC uses SC circuit? Does the ADC input have constant/or linear R/C/L/Z?
3. what are the requirement for linearity offsets and drifts?
4. ADC input type - single ended or differential?
4. Do you really need such fast opamp? - the higher power consumption and associated thermals could create headache even at the 6 1/2 digit AFE

[K-Zoltan]

Here is a drawing with 8.5 digit voltmeter I made.

[Echo88]

Did you read up on the HPM7177? The only real OSHW project that i know off that actually shows a complete project with measurements coming close to a true 8.5 digit voltmeter.
You will have to spend plenty of time/money already to design a good DCV analog front end for your ADC, so i assume there wont be time for I/R-measurements.
Do you have the means to measure the resulting specs like INL accurately enough, like multiple 3458A or JJA-access?

https://ohwr.org/project/opt-adc-10k-32b-1cha/wikis/home
If a high impedance analog frontend is needed you could copy the 3458A-frontend like i intend to do in a coming revision of my HPM7177-implementation, as suggested (not tested, work in progress) here: https://www.eevblog.com/forum/metrology/analog-frontends-for-dmms-approaching-8-5-digits-discussions/msg5034982/#msg5034982

[K-Zoltan]

Here is the nstrument I made

High impedance frontend I used opa1289 and is in a metal case heat to 40 deg. C In place of relays I used optoflash TLP240.
3458 is an old 35 years (or more ?) old instrument full with discrete components. Now there are much better IC than ampifiers with discrete components.

[dietert1]

For our Prema 6048 inspired design there is a voltmeter front end with a +/- 6V bootstrapped OPA189 or similar as single ended buffer, as the integrator is single-ended, too. There are three input relays for the two input polarities and null. The four ranges may become 24 V, 12 V, 2.4 V and 240 mV. While upper ranges are 1x buffered, for the lowest range the bootstrap gets turned off and there is 10x gain. I think the combination of a chopper-stabilized input amplifier with a relay to recalibrate null once the oven has reached stable temperature should be a good solution. The circuit preserves the "continuous integration" concept of the Prema.
Don't have measurements yet. Boards just arrived while i am writing.

Regards, Dieter

[Echo88]

Very interesting K-Zoltan. Can you share more of your design?

[Mickle T.]

Here is the nstrument I made

"Video unavailable. This video contains content from SME, who has blocked it in your country on copyright grounds" 

[2N3055]

Here is the nstrument I made

High impedance frontend I used opa1289 and is in a metal case heat to 40 deg. C In place of relays I used optoflash TLP240.
3458 is an old 35 years (or more ?) old instrument full with discrete components. Now there are much better IC than ampifiers with discrete components.

Am I confused, or what? There are 8 digits on display... That would make it 7.5 digit meter, or am I wrong.?

[Ole]

Am I confused, or what? There are 8 digits on display... That would make it 7.5 digit meter, or am I wrong.?

The Range shown on the thumbnail is the 10V range, which is resolved with 7 digits behind the period. Assuming the range goes only to 9.9999999V it would still be a 8 digit display (as there are 8 fully variable digits).
Assuming the range can go up to 12V it would mean that there are 8 fully variable digits and one that can either be a 0 or a 1.
The first digit, the one that can only be a 0 or a 1, is hidden because it is not needed.

[David Hess]

The CMRR could be a liniting factor for the linearity.  With typ. 130 dB this not enough to guarantee better than 0.3 ppm INL. However chances are that much of the CMRR is still linear - so from this side it can be just acceptable, though not great, when hunting for possible sources of INL.

It is not really practical because of all of the analog switches needed, however Intersil solved the CMRR problem by executing the automatic zero function at the common mode input voltage, so that the automatic zero also corrected the common mode rejection.  Siliconix did not and their designs suffered for it.

For a buffer it is relatively simple to use a bootstrapped supply and this way essentially eliminate the effect of the CMRR.

I would consider bootstrapping the input buffer for another reason also; it would allow for a gigaohm+ input resistance exceeding 15 volts.  Most designs are limited to 2 volts or maybe 10 volts, but 15+ volts is very handy and something I am looking for in my next multimeter purchase.

An alternative buffer would be a Zero drift OP-amp like LTC2057 or OPA189. These usually have very good CMRR and gain, at lest for DC and low frequencies.

I think using a zero drift operational amplifier as a buffer would be a mistake because the input bias current and input current noise will interact with the series input protection (and source impedance) to add offset and noise.

The offset voltage of 80uV I should be perfectly fine. but the tempco can possibly be better. The typical is actually +-0.2uV/C with a maximum of 1.2uV/c

The input offset voltage drift specification is tough.  Even my new favorite low input bias current precision part, the OPA140, has a maximum input offset drift of 1 uV/C, which is great for a JFET input but an order of magnitude worse than the best bipolar inputs.  Chopper parts solve this but have worse problems with high impedance inputs.

That means grading the input buffer for low drift, correcting the drift somehow, or correcting the drift with automatic zero which is how most designs handle it.  One place I worked did the first one with a test chamber and marked the top of the parts with the drift.

[dietert1]

One needs to do something about low frequency noise. If one does it with autozero e.g. 1 PLC alternating between unknown and null input, half of the input signal gets lost. If one does it using a chopper stabilized opamp, it supports continuous integration, yet the chopper frequency will probably be higher with more noise generated at the input.

I agree with K-Zoltan that we should try and use integrated circuits where possible. There is a large choice of chopper opamps, some with less input current than the OPA189. In the bootstrap scheme one can also try and compensate the input current to maybe reduce it from 100 pA to 10 pA. As i plan to run the meter inside an oven at constant temperature, there is a good chance to make the compensation work. Anyway, 100 pA at 10 V gives 100 GOhm and with compensation one can expect 1 TOhm.

Regards, Dieter

[Kleinstein]

There is usually no need to go for the super low noise AZ amplifiers. The input noise of the HP3458 is more like 50 nV/sqtz(Hz) assuming 100% integration. So one can get away with lower input current AZ amplifiers like AD8628, LMP2011 or MCP6V76 and still get a comparable or slightly better noise. These have less input bias and less current noise. However the lower bias types often only comes with a limited supply voltage (e.g. 6 V max) and thus kind of need bootstrapping the supply already for a 10 V range.  With suitable filtering at the input one can isolate it from variations in the input impedance reasonably well.
The very low bias types (max4238, ICL7650, LTC2055) are a bit on the high side with the noise.

Chances are one needs some luck with the amplifier bias and switch leakage to get at least partial compensation or good individual units.

The input resistance is more like a differential thing. So one has some input bias and than an input resistance describing how the input current changes with the voltage. So I would not call voltage range divided by input bias the input resistance.  One usually needs some filtering anyway to keep EMI out and as part of the ESD protection.

In my DMM circuit I have an AD8628 with a BS supply for the main input that works OK.
In my case I got some 6 pA bias and some 300-400 Gohm of differential input resistance with a large part of this likely from PCB leakage (changed with cleaning). For bias I consider this a lucky pick of the amplifiers and switches. Actual values can scatter even with the same types used. I have an MCP6V76 with a high voltage divider and this also works OK.

The choice of Az amplifier (e.g. Keithley 2000 / 2002, Datron 1271/1281 like) vs AZ switching (e.g. HP 3458 and most other HP) is between frequent chopping with small spikes in the AZ amplifier versus relatively low frequency (e.g. 2.5-25 Hz) but usually larger switching peaks. Both have there pros and cons.

[Echo88]

I assume the AZ-cycle time can be reduced pretty much when the first amplifier/buffer stage in the AFE (discret or not) can be kept at a stable temperature, like in this paper: https://arxiv.org/pdf/1708.06311.pdf
After the buffer youre free to throw AZ-OPs at it.

[Kleinstein]

The range for the auto zero cycle is usually pretty small:  less than 1 PLC is often problematic as mains hum can cause problems. Also many switching spikes are not that desirable. Without Az amplifier one usually wants to suppress much of the 1/f noise and much more than 1 slow reading (e.g. 100 PLC) is not practical. Often 10 PLC is used as a upper limit. So the main choices are some 1 to 10 PLC for the AZ cycle length, rarely more.

When there is a low drift (in generalle some kind of AZ amplifier) input buffer the AZ cycle behind it can often be 1 PLC, unless the ADC wants more (especially some older multi-slope ADCs). The JFET amplifier with stablilized temperature is more like an oddity and may still have 1/f noise or slow drift (e.g. from stress or aging) and may thus still want some AZ switching in front - maybe just with a rather slow cycle.

The main configurations to look at are:
1) AZ switching close to the input and than non AZ amplifiers (or just 1 amplifier) all the way to the ADC  (e.g. HP DMMs).
   This often needs some pre-charge cicuit to limit the swiching spike.
2) an AZ buffer at the input and than AZ switching after that followed by a non AZ amplifier (e.g. Keithley 2000 / 2002)
3) an AZ amplifier at the front and than AZ switching and a buffer or 2nd amplifier stage at the ADC input (e.g.  my DMM circuit, Keithey 2182)
4) an AZ amplifier at the front and than a low drift ADC (e.g. Datron 1281, likely SDM3065, Solartron 7081) with only rare Az switching - if at all
    Many of the SD-ADC chips have pretty low dirft and may allow this configuration

One may mix the cases, and not all input paths must look the same - though with most meters it is.
The case with an non AZ buffer at the input is more a thing for electrometers, not so much for a high resolution DMM.

[macaba]

If hyper-focused on a small part of the design, an integrated zero-drift amplifier would appear to make sense, however when considering the whole design, integrated zero-drift amplifiers are not suitable for the input amplifier on a 8.5d voltmeter design (and HP agreed). Designs that use zero-drift amplifier on the input are more like "low source impedance digitiser" rather than "voltmeter" (HPM7177 being a good example where it is continuously monitoring LHC magnets in a highly stable temperature environment).

(I'm going to use the term "chopper frequency" going forward, but this could easily refer to the frequency of non-chopper zero-drift mechanisms like autozero, correlated double sampling, and higher order nested zero-drift schemes, as true chopper topology amplifiers are rarely used anymore)

1. IC AZ has no control over the charge injection spikes. With a discrete design, it's easier to have precharge phases. Furthermore, because the chopper frequency of a discrete implementation tends to be lower (1NPLC for example), it's easier to observe the charge injection spikes during development.
2. IC AZ has high input current noise. Good luck measuring high value resistors. Current noise is usually proportional to the chopper frequency. Lower frequency = lower current noise. (therefore you can see the advantage of 1NPLC vs >100kHz...)
3. So the drift of one amplifier is solved... what about the whole signal path? ADCs have 1/f noise too. Even the AD4630 which claims "1/f noise is canceled internally" on the datasheet. So now there are multiple points of the signal chain doing their own zero-drift mechanisms which is a recipe for problems. IMO it's better to do chopping on the whole signal path as one, at a frequency you control.
4. There was mention of "half the input signal gets lost" - there are topologies that avoid this, though I don't think it's a big concern for DMM inputs to have a auto-zero scheme that halves the sample rate. For a modern DMM that only has an IC ADC (no integrating ADC), I think it's sensible to have 2 distinct modes of operation - "NPLC mode" where all the auto-zero/auto-cal mechanisms are enabled, and "Digitiser mode" where they are disabled (perhaps with a single correction at the point where you change modes, and automatically thereafter at any point where the internal DMM temperature has changed 0.1 degC, with an optional user override of this behavior when you absolutely must have a contiguous stream of samples, as in the case of HPM7177).
5. Once you have a discrete zero-drift mechanism in place, other advantages come in too - that analog switch that does the switching between "Input" and "0V" can have another input to a mux that allows the selection of other voltages (like REF+), ideal for self-calibration.
6. JFET front end (whether discrete or OPA140) already has single-digit pA input bias current. Far less compensation required, if any.

[tszaboo]

Context: I am designing an 8.5 digit ADC with surrounding voltmeter with a novel self-calibration technique as part of my final year project. (about which i will share but not until the project is finished).

As part of the ADC I need an input buffer and believe an ADA4625-1 unity gain buffer should be sufficient. Mostly because this is more about the ADC and getting a +-10V voltage digitized as accurately and precisely as possible. The following project would be about getting other functions such as I and R along with various voltage ranges but for now the ADC is the priority.

does anyone have any suggestions on the input buffer or should it be more than enough for the project at the moment?  Is there anything Im missing? or should this suffice?

My suggestion is to select another final year project. You will only have time to run 1 maybe 2 PCB iterations. There are a lot of pitfalls in designing a 8.5 digit AFE. University teachers don't grade or appreciate the difficulty of the problem, they grade the paper that you submitted. You need to worry about latex, sources, reading publications, and wrestle with MS Word. Not chasing nanovolts. You simply don't have time to do it right anyway, and you are expected to spend most of your effort on the paper, not the circuit
It's an interesting project, but not if you are graded, and not with deadlines. Maybe drop it to 6.5 digit, if you made this for yourself.

[iMo]

As I wrote earlier - would be great to develop a simple AFE with +/- 12V input range only, as a Proof of Concept.

Targeting complex designs with U/I/R capabilities in multiple ranges means man-years of work with many iterations, with a result nobody would be able to reproduce (for many reasons) or characterize.

Thus a bootstrapped OPA140 (for example), with some switch for calibration/zero, then a 1:10 divider with the final buffer to feed the ADC chip low impedance with a differential +/-1.2V.

I think having such a simple AFE with rock solid performance (which would be fully in pair with any single chip ADC we have got handy, like the ADS1263, AD7177, LTC2500-32, AD4630, etc) would be a great practical achievement here. Also for sahko's final year paper, imho..

[Kleinstein]

The integrated AZ OP amps are not that bad:
 They can use quite some extra effort (more elaborated than the simple precharge) and on chip matching can be quite good with little parasitic capacitance. Another point is that the AZ amplifier are usually chopper stabilized and thus switching with very low voltage at the switches.  So the individual switching spike from the AZ amplifier are considerably smaller than the spikes from switching with the full swing like in the HP meters AZ switching cycle.  Another point is that AZ switching usually uses a short break to let the spike decay - this can be good, if the decay is fast and also bad if the signal source is high impedance / capacitive and stretches the spike to extend beyound the dead time. With the dead time filtering the spike can be tricky as this is just the kind of source that stretches the pulse.

There are meters with discrete build chopper stabilized amplifiers too (datron 1281, Solartron 7081), that can use a moderately low chopper frequency. The reduction in the current noise is for the most part only with the square root of the chopper frequency. It is the input bias that about scales like the frequency.

[dietert1]

If hyper-focused on a small part of the design, an integrated zero-drift amplifier would appear to make sense, however when considering the whole design, integrated zero-drift amplifiers are not suitable for the input amplifier on a 8.5d voltmeter design...

Back to reality: The Prema 6048 was an 8.5 meter design using a chopper input amplifier instead of autozero and it is on par with the best HPAK meters, once you have the multiplexer, so one can recalibrate null without touching cables. Look for recent statements of RAX. My own experience is similar, except i want an ovenized/humidity controlled meter. At the same time one can try other improvements.

Regards, Dieter

[David Hess]

3. So the drift of one amplifier is solved... what about the whole signal path? ADCs have 1/f noise too. Even the AD4630 which claims "1/f noise is canceled internally" on the datasheet. So now there are multiple points of the signal chain doing their own zero-drift mechanisms which is a recipe for problems. IMO it's better to do chopping on the whole signal path as one, at a frequency you control.

Does anybody apply chopper stabilization to the whole signal path?

The high impedance buffer at the input is the largest contributor of noise before the ADC, and delta-sigma ADCs, at least the instrumentation ones, do cancel their own 1/f noise.  They even have the same input offset and input offset drift as chopper stabilized amplifiers built on the same process. (1)

Hmm, since the input divider effectively raises the input referred noise of the high impedance buffer, do electrometer style inputs where the input buffer is bootstrapped display lower noise because their divider is after the high impedance buffer?  This could be another reason to bootstrap the high impedance buffer.  I have not noticed that electrometers have lower noise than multimeters, but I have never had both to compare at the same time.

(1) Some delta-sigma converters intended for transducer measurement have a mode where they chop the excitation output with their inputs so they do chop the entire signal conditioning chain, and some multimeters do the same thing in 4-wire ohms mode.

[Kleinstein]

AFAIK the DA1281 and solartron 7071/81 use chopping the whole way - at least they can. The Prema 6048 also has only the one chopper amplifier in the input path. The ref path uses precision BJT parts, though and in a way that an offset there mainly effects the gain, not so much the zero point.  The point here is to have low drift not only for the input amplier, but also for the ADC.

Many other multi-slope ADC versions (e.g. the HP3458) have quite some drift and 1/f noise. So they need the AZ switching not just for the amplifier, but also for the ADC.
For the common ADC type with switching at the integrator input the offset drift is not just from the OP's, but also from resistor drift. So an AZ OP alone would not help much with the ADC drift.

An electrometer input with a high voltage range (e.g. some 100 V) may be lower noise than a more classic DMM with 1:100 divider and than an amplifier. Here it is not only the amplifier noise, but also the thermal noise of the divider resistor (e.g. 100 K at the low end have some 40 nV/sqrt(Hz) of noise).  For the comparison it still depends on the frequency to look at as the electrometers usually have quite some 1/f noise. For lower noise It would help to have less initial divider and than use a larger input range (e.g. +-20 V), even of this need an extra divider after the buffer. Also the usual :100 and x 10 for the 100 V range is not ideal.

[David Hess]

An electrometer input with a high voltage range (e.g. some 100 V) may be lower noise than a more classic DMM with 1:100 divider and than an amplifier. Here it is not only the amplifier noise, but also the thermal noise of the divider resistor (e.g. 100 K at the low end have some 40 nV/sqrt(Hz) of noise).  For the comparison it still depends on the frequency to look at as the electrometers usually have quite some 1/f noise. For lower noise It would help to have less initial divider and than use a larger input range (e.g. +-20 V), even of this need an extra divider after the buffer. Also the usual :100 and x 10 for the 100 V range is not ideal.

The reason I was thinking of an electrometer style input is that the divider following the bootstrapped high impedance buffer can be lower impedance, so have lower Johnson noise, while the bootstrapped buffer has the same noise as a non-bootstrapped buffer.

[dietert1]

.. Does anybody apply chopper stabilization to the whole signal path? ..

There are integrated chopper stabilized amplifiers with clock input. One can run several of them in sync, let's say input buffer, reference current source and integrator. Don't know whether the two devices in a OPA2189 run in sync. Thermal EMF between the amplifiers will still be left, so an oven is good to have.
If we believe the Zürich paper linked by Echo88, temperature controlled amplifiers may be good enough without autozero/chopper stabilization. With their 20 °C FET pair they got 100 nVpp into 100 sec integration time over several days. Don't know how this compares to the OPA189 mentioned above and what it means for 1 second integration time.

Regards, Dieter

[David Hess]

Don't know whether the two devices in a OPA2189 run in sync. Thermal EMF between the amplifiers will still be left, so an oven is good to have.

I have used chopper stabilized duals and I think they do run using the same clock because I never saw idle tones show up in the output when they were cascaded.  If they used separate clocks then there would be problems.

[dietert1]

A circuit sketch for a voltmeter front end with four ranges with a factor 2x pattern, e.g. 3 V, 6 V, 12 V and 24 V. It shows how to implement force-sense drive. In my opinion the factor 10 pattern of many commercial meters is a budget version, i mean in audio we also accept 6 dB headroom but not 20 dB.

Regards, Dieter

Edit: For this to work one needs a 2 x 4 MUX that is good for 24 V.

[Kleinstein]

A high resolution ADC can cover quite some range, so that the 1:10 steps are not that bad, even if one operates at only 10% of the range. More switches for the gain also add more leakage current and a divider for a gain of 2 has relatively high output impedance to make it sensitive to leakage and also adds some noise.
Finer spaced ranges may be a slight advantage with an ACAL procedure to measure the gain steps relative to each other: more but smaller steps may give slightly better accuracy and maybe a way to do extra checks.

In the implementation shown the leakage of the switches may be an issue for the higher ranges. The 4052 switch is only for a limited voltage.
It also depends a lot on how the ADC is build and this one looks rather specific for the Prema type ADC with contineous integration. In other version one needs to turn the input off or uses symmetry with the switch resistance also for the reference. It may in some cases be possible to have 2 ranges at the ADC (e.g. 5 V and 10 V) and than keep the more classic 1:10:100 as amplifier gain setting.

[dietert1]

To work with the AD7177, one can connect the lowest range resistor to ground and use its voltage instead of current, probably with a buffer plus an inverting buffer.

Regards, Dieter

[iMo]

This is a simplest front end I can imagine (I had a thread about it in past). What you may need in addition are the input switches for AZ and calibration..
Bootstrapped OPA140 (9V, 3.4mApp output current in this example), ultra low leakage input protection. LT5400 (18k/2k) divider, and differential buffer (2x ADA4528).
With +/-12V input you get 2.4Vpp differential low impedance output for the ADCs (CM is 2.5V).
Not elaborated in HW yet, however.

[MasterT]

Here is a drawing with 8.5 digit voltmeter I made.

Does not make sence to me. AD7177 does have internal buffers on inputs & references, so all it takes to make a nice voltmeter is to put 4:1 (7.5 : 2.5 MOhm) resistive divider. Money already payed for luxury. 

 Design of the AFE required with chip  ADC w/o buffers.

BTW, my tests with AD7172 shows that I can't improve internal buffers with external circuitry even using  best of the  best IC on the market. Moreover, any external front-end significantly degrade SNR, especially if it comes to AZ OPA.

[Kleinstein]

The internal buffers, especially at the input are not ideal. Especially the INL can be an issue. With the typical 3.5 ppm INL with the internal buffers the ADC is no longer that interesting for a high grade DMM.
A 7.5 M : 2.5 M divider at the input would also add quite some noise, from the Johnson noise alone and chances are the input switching would be slow with such a low source resistance. Such high resistors also tend to be not very stable.  So at the very least one would need a buffer at the input and than a lower resistance (e.g. 30K and 10 K ) divider for the input.  There are better buffer than the internal ones, though this is not a simple task.

The other point missing is that with only pseudo differential drive (1 side essentially fixed at a virtual ground) one only gets half the range and the INL may also be not as good (the INL specs are for full differential input signals). One can add differential drive, by moving the input low side = other input of the ADC.  It may be a bit hard to understand and can add some complications (e.g. with gain at the input and electronic switching for current ranges), but it is a nice working way to drive a differential ADC.
I don't have a full reverse engeniering of the SDM3065 front end, but it looks like it uses a similar system, to get a +-20 V input range with only a +-15 V supply.

[iMo]

..One can add differential drive, by moving the input low side = other input of the ADC.  It may be a bit hard to understand and can add some complications (e.g. with gain at the input and electronic switching for current ranges), but it is a nice working way to drive a differential ADC.
I don't have a full reverse engeniering of the SDM3065 front end, but it looks like it uses a similar system, to get a +-20 V input range with only a +-15 V supply.

Could you elaborate a bit?
Would this be the case you have mentioned?
Would be ~1k (or 500) seen by the ADC low enough?

[Kleinstein]

For a true differential drive one would drive the virtual ground to the inverse of the output of U1. This does not have to be super precise as the error there would only cause a small common mode signal to the ADC that is reasonably well suppressed.

It depends on the ADC how low the driving impedance should be. For the internal buffers 1 K and even 10 K should be OK. Without internal buffers 500 Ohm may be OK, but not ideal (e.g. higher INL and gain error) - one has to check the ADCs datasheet on this. So one may need buffers between the divider and ADC.


The BS supply as shown for U1 may be boarderline when it comes to stability against oscillation. Usually the BS supply part should be slowed down a bit. So one may want some RC filtering before the bases of the transistors. It may work in the simulation, but this could be due to a bug in quite some OP models that don't properly handle a moving supply and use a GND reference instgead of the true supply somewhere in the model.

[iMo]

For a true differential drive one would drive the virtual ground to the inverse of the output of U1. ..

I think the ADC in above v42 (and below v42a) sees the inputs truly differential.. The ground there is the ADC ground.
Or am I mistaken somehow?
Below v42a with some stability improvement (and yes, LTSpice has shown oscillation with some inputs without the BS compensation, but primarily the ADC input is the case we have to solve)..

[Kleinstein]

The last circuit produces the differential drive by moving the GND point around. So the ADC's supply would have to be bootstrapped relative to the GND symbol and the GND symbol is not the power supply ground.  One could do it this way, but would not get the relatively large possble input range (e.g. 20 V) for the supply.

[iMo]

What about this config.. (v43)..
Input +/- 20V
Output +/-2V diff
Vcc +/-15V
LT5400 18k/2k divider (or 4.5k/0.5k with more current off the opamps).

[Kleinstein]

That circuit is about what I suggested, with the extra inverter. Chances are one would need some extra capacitance (e.g. 1 nF range) in parallel to R11 to slow down the inverter part a little to reduce ringing / gain peaking. Due to the divider the neg side of the ADC signal now moves too much and would also need a divider. So the divider should not be 18 K and 2 K , but more like 9 K : 2 K : 9 K with the ADC signals over the 2 K resistor. The AD7177 has a FS range of up to +-5 V and the divider would thus ideally be more like 1:1:1  ( 15 V FS range) or 3:2:3 (20 V FS range) and not 9:2:9.

The OPA140 is a good OP-amp, but may still want some way to check it's offset or do auto zero switching at the input.
Another point is that is can be tricky to add gain for lower voltage ranges.

[iMo]

To maintain the low output impedance and the divider ratio and the low opamp's output current - that is not an easy task with the two opamps, imho..
AZ input switch - any suggestion, btw?

PS: below with the square wave 40Vpp. You may see with DC the output error is much smaller compared with the 5Hz sine wave. I wonder how the big boys handle the propagation delay through all those (RC compensated) opamps..

[MasterT]

1.
The internal buffers, especially at the input are not ideal. Especially the INL can be an issue. With the typical 3.5 ppm INL with the internal buffers the ADC is no longer that interesting for a high grade DMM.

2.
A 7.5 M : 2.5 M divider at the input would also add quite some noise, from the Johnson noise alone and chances are the input switching would be slow with such a low source resistance. Such high resistors also tend to be not very stable.  So at the very least one would need a buffer at the input and than a lower resistance (e.g. 30K and 10 K ) divider for the input.  There are better buffer than the internal ones, though this is not a simple task.

3.
The other point missing is that with only pseudo differential drive (1 side essentially fixed at a virtual ground) one only gets half the range and the INL may also be not as good (the INL specs are for full differential input signals). One can add differential drive, by moving the input low side = other input of the ADC.  It may be a bit hard to understand and can add some complications (e.g. with gain at the input and electronic switching for current ranges), but it is a nice working way to drive a differential ADC.
I don't have a full reverse engeniering of the SDM3065 front end, but it looks like it uses a similar system, to get a +-20 V input range with only a +-15 V supply.

1.  Internal buffers of the AD7177 as good as ADC itself. Picture below. About 1ppm at the best, so I dn't know if it's any good for 8.5, more like 6 digits?

2. Regarding stability 7.5 M resistors, 75x100k resistors matrix is still lower in cost than AFE.
  Input buffers should have ultra low bias current to work with 10 M (in case not divider, but output inpedance of the voltage source measured), and here we have complication, I'm sure overall stability/ linearuty /noise of the OPA189 is much worse when interfaced with 10M, than chiepest 7.5 M resistors one cat get. There was a topic recently regarding problems with input bias AZ amps, OPA18x.

3. This is only argument I agree, differential drive - verse INL. But still this sollution needs to be checked mathematicaly  if it worth to buld SE-DIFF converter if ADC never break 1 ppm INL in any way. And what is the difference would be since AD doesn't provide SE INL data, there is a chance that would not be any difference at all

[David Hess]

AZ input switch - any suggestion, btw?

I am just thinking out loud here.

If the switching is also bootstrapped, then it does not need to handle high voltages, *and* zeroing of the input buffer can occur *at* the common mode input voltage removing all common mode errors like the old Intersil designs.  The control signals will need to be level shifted, but that is easier than implementing a low leakage high voltage switch.

Of course with bootstrapping there should be no common mode errors anyway, but is that really the case?  As I recall, the common mode rejection of the operational amplifier will be multiplied by the open loop gain in this case, so nonexistent.

I wish there was a way to remove the flicker noise.  There are dual path designs which do, but then the input bias current of the chopper is added to the input bias current of the buffer defeating the advantage of the buffer.  The OPA140 has such a low input bias current that several could be used in parallel to make some improvement.

[Kleinstein]

Using only pseudo differential input limits the votlage range to +-2.5 V and thus limits the SNR. In addion the single ended mode may well have even order INL parts. The true differential mode tends to suppress the even oder INL contributions as seen in the INL curves with a relatively point symmetric curve and thus little even order INL part. The data sheets tend to show the good points and if not extra bad or normally expected more leave out the weak points.

The typical specs are 1 ppm without the buffer and 3.5 ppm with the buffer. The difference may not be that visible in the graph though, but the curve without the buffers still look a little better.
The Cern digitizer showed even better INL, at least for positive voltages. So the 1 ppm from the datasheet may be based on a not so ideal layout / circuit. One weak point the switched capacitor ADCs is that the ADC chip itself is only part of the solution and the buffers/amplifiers for the signal and reference can effect the INL, noise and drift quite a bit. This especially means that one still should check the INL of the actual circuit unless it is a 1:1 copy of the test circuit used for the specs, which is often not shown in detail. The requirements with the reaction to short charge pulsed are not that easy to tell from specs alone - it may need real world tests.

I totally aggree that a 1 ppm INL spec is not really what one expects at 8.5 digits, still better than most 6 digit meters. So maybe more like a compromise 7 digits. 3.5 ppm is more like 6 digits and not even a good one.

At the high end and already at 6 digits one usually wants a high impedance (e.g. > 10 Gohm)  input impedance. So a 10 Mohm input divider for all ranges is not really an option. It is kind of needed for the high voltages, like >20 V where it gets tricky to build an amplifier. So I don't see a point in a 10 M divider from 10 V to 2.5 V.  Using multiple resistors combined still does not solve the problem with possible leakage on the PCB.  Its not much leakage to get a few ppm error to a 7 M resistor. Up to some 20 or 25 V there is the option to use a driven low side and conventional +-15 V supply switches.  Another point is the input impedance of the buffer - this may not be that linear compared to some 2 Mohm from the 7.5:2.5 M divider output. Already with a more conventional 9.9 M + 100 K divider the input impedance of the amplifier / buffer and if present FET switches can be an issue.
So even there the OPA189 is likely not a good choice. More suitable may be an MCP6V76 or AD8628 with a bootstrapped supply (to get very high input impedance).
For the signal source one often still has way less than 10 M, usally even less than 100 K. With common > 10 Gohm specs one would need less than 10 K to keep at least 1 ppm accuracy for sure.

[Kleinstein]

If the switching is also bootstrapped, then it does not need to handle high voltages, *and* zeroing of the input buffer can occur *at* the common mode input voltage removing all common mode errors like the old Intersil designs.  The control signals will need to be level shifted, but that is easier than implementing a low leakage high voltage switch.

Of course with bootstrapping there should be no common mode errors anyway, but is that really the case?  As I recall, the common mode rejection of the operational amplifier will be multiplied by the open loop gain in this case, so nonexistent.

Bootstrapping the switches only works part ways. When using classical AZ switching like in the HP meters there still needs to be a switch to bock the full voltage. One can use bootstrapped switches for the first part / precharging phase at least. In the parallel thread
https://www.eevblog.com/forum/metrology/analog-frontends-for-dmms-approaching-8-5-digits-discussions/msg4454926/#msg4454926
there are suggestions and even so prilimary test results that look very promissing. I see the main point in reducing the switching spike, which can be quite anoying and hard to compensate with classical switches.
For a chopper stabilized amplifier one can use bootstrapping the the switching part, e.g. as used in the Datron 1281 and likely internal in many of the high voltage AZ OP-amps like OPA189.

The bootstrapped amplifier supply should essentially avoid the CM error and also increase the input impedance (voltage dependent input bias current). Bootstrapping is relatively easy for a buffer, but a bit more tricky, but still possible for an amplifier.

[MasterT]

~~~~~~~~~~~~~~~
At the high end and already at 6 digits one usually wants a high impedance (e.g. > 10 Gohm)  input impedance. So a 10 Mohm input divider for all ranges is not really an option. It is kind of needed for the high voltages, like >20 V where it gets tricky to build an amplifier. So I don't see a point in a 10 M divider from 10 V to 2.5 V. 

What you are saying, it's very nice to have:
 1G input impedance + ultra linear + low noise bandwidth & 1 /F  .
The problem is you can't have all 3 sides.   Dual stages (non-inverting high impedance buffer followed by low voltage second stage right in front of the adc and 1/4 divider in between stages or inverting second stage) degrade 1 /F and low noise down to not acceptable level. AZ OPA is not a cure, since it introduces wide bandwidth noise and 1G is in question as well as linearity - chopping frequency may distruct adc completely. Building AZ out of discrete parts is also not an option, there are no switches w/o injection current low enoght, and there is no access to internal clock chain of the adc.
 
 So my point is you can't make buffer that outperforms internal, simply because it's synchronized to internal clock structure of the adc. It's "integrated" in the processing signal path.  And it's have switches/ matrix in front of it, providing offset/ full scale / linearity calibration capability whenever  end user like.

[iMo]

..thus it seems no new particles will be discovered at CERN after the installation of the HPM7177 units.. 

[Kleinstein]

The highest accuracy is only needed and achievable with a relatively low source impedance (e.g. < 10 K to maybe 100 K). If the buffer is >> 1 Gohm input impedance this does not mean it must also work with a comparable source impedance. Even if it does not work well with a 1 M source this could be acceptable. There would be the option to have multiple inputs for different sources.

A configuration with buffer - lower resistance 1/4 divider - buffer (ADC internal or external) does not degrade the noise performance very much, though the resistors at the divider add some noise and to low in resistance can run into thermal INL issues.

I see 2 ways to implement this:
1) A bootstrapped AZ OP-amp (e.g. AD8628) at the input and if needed have extra switching (ADC internal or external) between the divider and buffer.   
2) Switching a the front and than use non AZ buffers (e.g. OPA140 with BS supply and maybe current driver support).

The first way is about how the Keithley 2002 and Datron 1281 work on there 20 V range, though with a multislope ADC and 1/2  divider.
The Keithley 2002 does however suffer from some LF noise: I am still not sure about the origin: could be the AZ part of the input buffer, thermal fluctuations or a software oddity in how AZ is handled.

I have tested the AD8628 with some moderate RC input filtering and this is sufficient to largely isolate the AZ amplifier from the source impedance. It still works OK with a 10 M source - not great, but still good enough. The measure input impedance including protection and switching at the input is in the 300 Gohm range (that is some 3 pA of change in the bias per 1 V change in the voltage). The divider and 2nd buffer would isolate the input buffer from the ADC. So one should not expect interference in either direction. Switching at the relatively low resistance divider should be no problem.
I still have some LF noise (~ 20 nV, likely thermal and supply), but this is not an issue for the 20 V range, mainly for 200 mV.

The 2nd way is how the HP3458 works, though with only 1 amplifier stage and no divider, as there is only a 10(12) V range just like the ADC provides. Switching at the input can suppress LF noise and offsets from both buffer stages.  The somewhat tricky part can be to keep the switching spike small, so that it works with more sensitive sources. The full swing switching and dead time makes filtering a bit problematic.

[David Hess]

So I don't see a point in a 10 M divider from 10 V to 2.5 V.

A 10M input resistance on all ranges, including the low voltage ones, can be important for consistency of measurements.  It is disconcerting when a range switch from say 2 to 20 volts results in a change of reading way outside of the accuracy specifications because the source resistance was not zero ohms.

I ran into this most recently when using an external high voltage divider probe which expected a 10 megohm input resistance on the voltmeter.  I had 4 voltmeters and 2 results because one of them had a high resistance input instead of 10 megohms.  When that one voltmeter was manually switched to its 20 volt range, forcing a 10 megohm input, then all 4 readings were consistent.

[MasterT]

..thus it seems no new particles will be discovered at CERN after the installation of the HPM7177 units.. 

Have no idea.
What I do know, is how de-glitch circuits operates. Here is some theories,
https://www.allegromicro.com/en/insights-and-innovations/technical-documents/hall-effect-sensor-ic-publications/chopper-stabilized-amplifiers-with-a-track-and-hold-signal-demodulator

 To null out charge injection spickes , sampling by adc must be in correct phase relation with chopping circuitry. Period.
 ADC's Internal buffer has great advantage to synchronize all processes. External AZ OPA, even the good one like max44251  (I'd think about crappy AD8628 as a joke),  configured as G=1 buffer has a few MHz bandwidth. There is no way to limit this band with G=1, so accumulated noise  jump up in x1000, and excellent 5.9 nV /sqrt(Hz) becomes 6 uV-RMS, or 36 (!!!) uVp-p. Now compare to about 50 nVp-p that internal buffer has.
 

 

[iMo]

So I don't see a point in a 10 M divider from 10 V to 2.5 V.

A 10M input resistance on all ranges, including the low voltage ones, can be important for consistency of measurements.  It is disconcerting when a range switch from say 2 to 20 volts results in a change of reading way outside of the accuracy specifications because the source resistance was not zero ohms.
..

.. for example the Fluke 8588A has got 10Meg only (I tried to switch it to Hi-Z with no success)..

[Kleinstein]

To null out charge injection spickes , sampling by adc must be in correct phase relation with chopping circuitry. Period.
 ADC's Internal buffer has great advantage to synchronize all processes.

Ideally one would have the ADC sampling syncronized with the chopper amplifier. However with relatively small spikes and some filtering between the AZ amplier and the ADC (e.g. the passive RC AA filter) one can get away without this with little penalty. The spikes from integrated chopper OPs are quite short and already reduced by the limited BW of the amplifier.
Using a SD ADC chip with an AZ amplifier is nothing new or special. It is regularly done with usually little problems.
The synchronization gives a slight advantage in this respect to the ADC internal buffer. Still the buffer also has limitations, e.g. with the INL, where external buffers can be better.

External AZ OPA, even the good one like max44251  (I'd think about crappy AD8628 as a joke),  configured as G=1 buffer has a few MHz bandwidth. There is no way to limit this band with G=1, so accumulated noise  jump up in x1000, and excellent 5.9 nV /sqrt(Hz) becomes 6 uV-RMS, or 36 (!!!) uVp-p. Now compare to about 50 nVp-p that internal buffer has.

The noise in the full BW of the amplifier does not really matter. The SD ADC in combination with the AA filter at it's input limit the bandwidth to a low value. One may have to take care that the chopper spikes are not causing aliasing though. So the RC filter at the ADC input is important, especially with AZ amplifiers/buffer that may have extra noise in the relevant frequency range.

The point with high input impedance is for the buffer before the divider - the 2nd buffer (may be 2 for pos and neg input) is a different thing. For the input side the max44251 or OPA189 are more like a poor choice for a more conventional DMM, as they have too much current noise (e.g. 600 fA/sqrt(Hz) for the max44251) and input bias. Here one needs some compromise and the AD8628 is about at a suitable point for a normal DMM  ( ~ 22 nV/sqrt(Hz) , ~ 40 fA/sqrt(Hz) and some 10 pA range input bias). The data-sheet value for the AD8628 current noise seems to be too optimistic - a common thing with AZ OP-amps. On the other side the bias specs often tend to be a bit pessimistic to cover a range of supply and CM voltages and input impedances. With care on about equal impedance one can often get a better bias current.

For the buffer after the low impedance divider one would prefer less voltage noise and current noise and bias are less relevant. Here the max44251 may be suitable but possibly overkill.
The buffers directly at the ADC may also be non AZ types, when an additional layer of switching (could also choose divider ratios) is used.

[David Hess]

I was thinking about how to correct the drift and 1/f noise of a bootstrapped OPA140, or any other low input bias current part.  I wonder if a discrete chopper design is feasible using photo-FETs.  The H11F1 series is what comes up now if you do a search however I thought I remembered higher performance 3N parts with better leakage.  The datasheets for the H11F1 series only list worst case values so it is not clear how well they really perform.

Here one needs some compromise and the AD8628 is about at a suitable point for a normal DMM  ( ~ 22 nV/sqrt(Hz) , ~ 40 fA/sqrt(Hz) and some 10 pA range input bias).

When you write "normal DMM", do you mean like 4-1/2 digits or non-electrometer input?

4-1/2 digit DMMs can easily get by without chopper or even automatic zero.

[Echo88]

You can use PhotoFETs for chopping or Autozero, but their switching times are typically in the µs-region.
H11F1 produce considerable offset voltage, see the document attached in https://www.eevblog.com/forum/metrology/measurements-of-leakage-current-and-offset-voltage-on-some-optofets-and-relays/ "A BILATERAL ANALOG FET OPTOCOUPLER.pdf"Figure 8
Leakage of generic PhotoFETs like AQW210S or similar can by suitably low, check my measurements in the document "OptoFETs realigned.xlsx".
The document also contains H11F1 offset voltage measurements.

[Kleinstein]

I was thinking about how to correct the drift and 1/f noise of a bootstrapped OPA140, or any other low input bias current part.  I wonder if a discrete chopper design is feasible using photo-FETs.  The H11F1 series is what comes up now if you do a search however I thought I remembered higher performance 3N parts with better leakage.  The datasheets for the H11F1 series only list worst case values so it is not clear how well they really perform.

Here one needs some compromise and the AD8628 is about at a suitable point for a normal DMM  ( ~ 22 nV/sqrt(Hz) , ~ 40 fA/sqrt(Hz) and some 10 pA range input bias).

When you write "normal DMM", do you mean like 4-1/2 digits or non-electrometer input?

4-1/2 digit DMMs can easily get by without chopper or even automatic zero.

With normal I meant not an electrometer input for very high source impedance and also not a nV meter for very low noise and thus also low (e.g. < 1 K) source impedance.
Noise wise an amplifier gets the best noise figure it the source impedance is equat to the ratio of voltage noise to current noise. For the AD8628 this is at some 500 K, the LCT2057 at some 70 K and the max44251 or ADA4522 is more suiteable for some 10 K.
The other point is having a input bias in the < 50 pA range, but no need to aim for < 1 - 5 pA as with electrometer inputs.

Attached is a graph from the Keithley Low level measurement Handboock, that shows the destiction.

[Echo88]

While were at it: Like iMo pointed out the 8588A indeed seems to only have 10M and 1M input impedance. No >=10G as is standard for >= 6.5 Digit tabletop DMMs.
Are they trading performance for Zin or did they just cheap out on the analog frontend?
https://us.flukecal.com/literature/product-literature/specifications/8588a-product-specifications

[Kleinstein]

They have 1 M, 10 M and auto. Here auto is > 1Tohm up to 10 V range - see page 3.  Not sure which setting is standard, but I would expect auto.

[Echo88]

Ah indeed, doh. page 11. I was irritated by them also using "Auto" in the 100/1000V-range, where its suddenly meaning a different input resistance.

[iMo]

They have 1 M, 10 M and auto. Here auto is > 1Tohm up to 10 V range - see page 3.  Not sure which setting is standard, but I would expect auto.

When toggling between 1M, 10M, auto, I would select 10M.. What we did.. 
We do not read manuals..

In my first schematics V40 above I have there

OPA140->18k/2k divider->2xADA4528->ADC_diff_inputs

How to wire that exact config such I get the V44 (with the increased input range)?

[Kleinstein]

The current V44 version has 3 K 2K 3 K and gives a +-20 V FS range. Actual resistor should likely be a bit higher(e.g. 5 x)  to avoid to much thermal INL.

A more practical version could be 20 K 10 K and 20 K which could allow for a theoretical +-25 V range. This may need a little more than +-15 V supply though to really get all the way to the extremes.
One could get the resistors from 8 x 10 K  also split over 2 arrays (the 10 K in the center would be 2S2P for this).
The divider choice depends on the targeted use. Also a 15 V range or maybe a ADC ref of a little less than 5 V (e.g. 4 V) may make sense.
The inverter for the neg side may use a bit larger resistors or even also use the resistors from the signal divider with a center tap in the middle.
With the still relative small resistors the loading of the amplifier can be an issue to cause thermal INL.

The amplifier for the input also depends on the needs. Beside the OPA140 for very low bias, but some drift, also an AD8628 or similar could make sense if one wants an zero drift front end at the cost of higher bias.

[David Hess]

You can use PhotoFETs for chopping or Autozero, but their switching times are typically in the µs-region.
H11F1 produce considerable offset voltage, see the document attached in https://www.eevblog.com/forum/metrology/measurements-of-leakage-current-and-offset-voltage-on-some-optofets-and-relays/ "A BILATERAL ANALOG FET OPTOCOUPLER.pdf"Figure 8
Leakage of generic PhotoFETs like AQW210S or similar can by suitably low, check my measurements in the document "OptoFETs realigned.xlsx".
The document also contains H11F1 offset voltage measurements.

Thanks for the link.  That offset voltage is a killer and 100 times greater than I expected.  So much for that idea.

The alternative might be 3N, SD, or JFET devices with external isolated drive to reduce charge injection.

[Kleinstein]

AFAIR the Keithley 2182 nV meter uses  pairs of 2N7000 FETs and photovoltaic drive for switching. This looks tempting but there is still a chance to get charge injection switching spikes. Compared to a Photomos switch this allows to separate the LED in the coupler as a heat source from the FETs.
The ready made photomos switches may still be good enough - I have not seen much offset and the HP34420 nV meter uses some in the signal path. So at least some types seem to be OK when it comes to parasitic thermal EMF. The separate build version is not necessay better if the layout is not good. I got a few µV ( AFAIR some -1 µV and + 4µV)  of thermal offset for that type of circuit.

[David Hess]

The ready made photomos switches may still be good enough - I have not seen much offset and the HP34420 nV meter uses some in the signal path. So at least some types seem to be OK when it comes to parasitic thermal EMF. The separate build version is not necessay better if the layout is not good. I got a few µV ( AFAIR some -1 µV and + 4µV)  of thermal offset for that type of circuit.

Given the magnitude of 100s of microvolts, there is more to it than thermal EMF.  I suspect exposure of any junction isolation is allowing the photoelectric effect.

AFAIR the Keithley 2182 nV meter uses  pairs of 2N7000 FETs and photovoltaic drive for switching. This looks tempting but there is still a chance to get charge injection switching spikes. Compared to a Photomos switch this allows to separate the LED in the coupler as a heat source from the FETs.

Some electrostatic shielding should go a long way.

I would like to try it with pulse transformers but that makes avoiding charge injection even more difficult.

[Echo88]

Jep, afair the big voltage offset with the H11Fx indeed also seemed to me like its related to photoeffects instead of TEMF.
If i understand it correctly controlling a JFET/MOSFET via isolated source or not is irrelevant. The changing gate voltage produced by the internal solarcell should produce a charge injection effect via its Cgd.
Dont share my opinion? Conduct a lobotomy on a PhotoFET by carefully drilling a hole into its side till you hit the brain...err transparent jelly that encloses the LED-solarcell combination inside the Epoxy case and stick a lightpipe into it to control the PhotoFET via external light source. I have such a guinea pig laying around on my table but havent dont any charge injection tests with it.

Normal MOSFET based PhotoFETs like PVA/AQV/AQW can produce very low offset voltage, at least thats what i measured:
PVAxxxx OptoFET at 1mA LED Drivecurrent: low TEMF ~25nV
PVAxxxx OptoFET at 2mA LED Drivecurrent: low TEMF ~50nV

[iMo]

Now imagine this rather extreme  spec for the AFE (and the ADC):

a. 10Meg input only
b. only positive input voltages - from 1.0V to 15V DC - in one single range
c. 7.5+digits resolution at 100-1000NPLC
d. AZ_opamp_input_buffer->low_imp_divider->ADC_buffer(?)
e. Gain Calibration switch at the input_buffer's input.

I think this covers 98% of activities people in this section actually do - they want to measure/check their references (1V/2.5V/5V/7V/10V/14V) from time to time.

No need to try to copy the high_end gear with all their specialties (rather a nonsense, imho)..
No need to go to <1000mV levels/ranges - no null meter requirement..
No need to measure negative voltages..
No need to have >10G input impedance..
No need to digitize fast AC signals..

How this spec would affect (or simplify) the design of the AFE, provided the ADC is the differential ADC (like the 7177, 1263, 2500-32)??

[Kleinstein]

The AD7177 can give 7.5 digit resolution already with some 1-4 PLC. With very good resolution a single range can go a long way. Noise wise one could still be comparable to a lower end 6 digit meter (K2000 or 34401) in the 100 mV range. To some degree overkill at the ADC can save on extra ranges, though this would than be more a 6 digit meter (also with a less accurate reference) using SW scaling for the lower ranges.

Going only 1 range simplifies things, especially in the system with the driven low side for a differential ADC (e.g. AD7177). So the configuration with a 3 resistor divider and driven low side (e.g. the V44 version). The range is naturally for both polarities. It is still not too bad (some not so critical CMOS switching, like a DG409)  to add a range (e.g. 5 V or a little less) with no extra attenuation and thus better stability. This may than look a little like the front end of the Sigilent SDM3065.  A point that can be a bit tricky is a way to measure the own reference and thus way check the ADC gain, reference divider and range setting divider. This part may need extra effort, like a charge pump stage.

There is no need to go for a 10 M only input - this makes not much sense and would be a serious limitation. At least for not so high voltages it is a simple relay to connect a 10 M higher voltage divider or not.
It would be more to skip the 10 M input impedance option and be high impedance only. At least the 100 Gohm range should be easy to reach.

[MasterT]

External AZ OPA, even the good one like max44251  (I'd think about crappy AD8628 as a joke),  configured as G=1 buffer has a few MHz bandwidth. There is no way to limit this band with G=1, so accumulated noise  jump up in x1000, and excellent 5.9 nV /sqrt(Hz) becomes 6 uV-RMS, or 36 (!!!) uVp-p. Now compare to about 50 nVp-p that internal buffer has.

The point with high input impedance is for the buffer before the divider - the 2nd buffer (may be 2 for pos and neg input) is a different thing. For the input side the max44251 or OPA189 are more like a poor choice for a more conventional DMM, as they have too much current noise (e.g. 600 fA/sqrt(Hz) for the max44251) and input bias. Here one needs some compromise and the AD8628 is about at a suitable point for a normal DMM  ( ~ 22 nV/sqrt(Hz) , ~ 40 fA/sqrt(Hz) and some 10 pA range input bias).

  Current noise is not relevant, since we are talking about DC application. Setting 0.1uF between input and ground reduce BW (bandwidth) to to sub-Hz.  Voltage noise,  has 1-10 MHz BW.

 Don't bother to replay, I'd keep my ignored list updated.

[David Hess]

If i understand it correctly controlling a JFET/MOSFET via isolated source or not is irrelevant. The changing gate voltage produced by the internal solarcell should produce a charge injection effect via its Cgd.

There is still common mode electrostatic coupling, hence my comment about electrostatic shielding.  Optocouplers often include electrostatic shielding, but not all of them.

I was thinking that for a magnetically driven FET, a center tap on the secondary of the pulse transformer could be driven by a guard to reduce electrostatic coupling by removing any common mode variation.  Tektronix did something like this in some of their 7000 series plug-ins for sample-and-hold amplifiers but without the center tap because they did not need that level of precision.

Normal MOSFET based PhotoFETs like PVA/AQV/AQW can produce very low offset voltage, at least thats what i measured:
PVAxxxx OptoFET at 1mA LED Drivecurrent: low TEMF ~25nV
PVAxxxx OptoFET at 2mA LED Drivecurrent: low TEMF ~50nV

Yes, but those are not available so might as well not exist.  At least I have not found these parts that you are referring to, and if they are SSRs, then I can do better with my own design.

a. 10Meg input only
d. AZ_opamp_input_buffer->low_imp_divider->ADC_buffer(?)

My own experience is that those two requirements are contradictory because of excessive input bias current, input current noise, and charge injection, but maybe modern parts allow it.

[Kleinstein]

Some of the modern AZ OP-amps are OK for a high impedance buffer. They still need some filtering with maybe a few 100 pF to ground. This would usually not be the super low voltage noise types (OPA189,AD4522 or similar), but more intermediate types like AD8628, LMP2011, MCP6V76 or OPA387 with often acceptable bias and current noise. Worst case one may have to select for low enough a bias.
They won't be ideal for 10 M source impedance, but still not terrible and the relevant impedances for a DMM are more like < 100 Kohm, and for a meter with only 10 M input resistance more like < 1 K anyway.
One usually does not care what an open voltmeter input reads and how noisy it is under this condition.
If really needed one could offer multiple inputs for different source impedance ranges, including an electrometer grade input and maybe one for low noise (more nV meter like) on the smaller votlage range.


The switching with optical driven MOSFETs is an interesting option mainly for higher voltages (e.g. up to 1000 V with some types). Usually they have 2 back to back FETs in series and if they don't switch at the same level one can still expect quite some charge injection pulse even with isolated drive. So I don't see them as a great option for the AZ switching at the input. This is more like a solid state relay replacement and maybe part of the protection.

For low glitch switching I would suggest using a pre-charge phase with bootstrapped switches. This part only switches between the actual input and a low bias buffered input signal. So the switch works at essentilly zero voltage across the switch and with fixed CM level to allow a fixed trim of the charge spikes. They can thus use a relative small gate signal (e.g. -5 V for JFETs or 3-5 V supply CMOS switches). Actual switching between the input (or buffer signal) and zero is than a 2nd set of switches, e.g. together with an input multiplexer. While switching here the actual input is isolated.
Normally there are only 2 or maybe 3 critical inputs that would really need the pre-charge part. So the extra effort for a separate pre-charge part per critical input is not that large.

The switching scheme of meters like the HP3456 or 3458 are more like input mux and than precharge switching as a 2nd step, so the other way around. This way they need the precharge part only once, but requires the compensation of the gate charge for a variable voltage and with higher voltage switches. This gets tricky as the gate capacitance is nonlinear. So the compensation can only be approximate, or needs a voltage dependent correction. This may be the reason the the rather complicated DAC part to trim the charge compensation in the HP3458 - could still be just a fixed trim.

[Echo88]

@David: The PVAxxxx refer to the many variants i tested in the "OptoFETs realigned.xlsx", for example PVA1052/PVA1054/PVA3054 etc. Many are obsolete as marked in the table, but there are also nice ones like CPC1017N or AQW210S.
Yes, apart from the H11Fx (H11F1/H11F2/H11F3) all OptoFETs/PhotoFETs or whatever they are called are optically controlled MOSFETs/SSRs.