integrator for multi-slope/charge balance ADC

[miro123]

I am considering starting a project involving self-built integrating ADCs and have several questions. To provide context, I'll first explain my setups and goals.

Test Setup - Common Parts
Vref: Provided from ADR1399
Test Voltages: +7V, +5V, and multiple GNDs
Analog Switches: Utilized in the setup
Control: Managed by an STM32G474. I know this part and I can squeeze every nanoseconds from available periphery
Output Monitoring: Conducted using a DMM6500 high-speed digitizer
Test Setup - Adjustable Part
Testing different integrator structures
Testing various switch types and supply voltages (This part might be unnecessary; see the Goals section for more details)
Goals
  Learning Phase:
      Understanding how integrator parameters and ADC structure affect performance (noise, linearity, stability, etc.)
  Integrator Characterization:
Building an integrator model to linearize the physical integrator
Switch Characterization:
Developing a switch model to determine injection, leakage, etc.
Questions
Integrator Types: What types of combined integrators are used in Multi-slope and charge balance ADCs? Kleinstein and Jaromir discuss using a kind of HP34401 Multi-slope3 integrator. I am interested in exploring modern electronics like Multi-slope4 high-speed ADCs.
Integrator Output Swing: What are the reasonable ranges for integrator output swing (Vmax, Vmin)? Are these voltages dependent on the type of capacitor used?
Capacitor Types: What types of capacitors are typically used? I assume COG/NPO for modern designs, while older slow-speed designs used foil capacitors. Is this correct?
I appreciate your time and expertise in addressing these questions.
Best regards,
Miro

[Kleinstein]

For the capacitor the choice is relatively easy. Good ceramic capacitors (e.g. TDK C0G) get lower dielectric absorbtion than most film types (maybe except PTFE) and they are small and affordable in the usual size needed (e.g. < 10 nF) for a multi-slope ADC.

For the integrator swing, more swing allows for a smaller capacitor and less voltage noise for the final / initial charge. If this is really relevant depends - with 1 PLC and slower it often is not that imporant.
Classical the swing was some +-10 V max, so that amplifiers with a +-15 V supply were sufficient. I would not consider the swing a very important parameter. For tests it is always helpful to have some headroom for variations. A small integrator capacitor also makes parasitic capacitance more relevant.

For the actual integrator the logic choice today is a combination of 2 OP-amps, to keep the input voltage really close to zero. This is one precision OP-amp and a fast amplifier for the output. I see no more need for the 3 amplifier version as in the 3458, as there are now fast enough precision amplifiers (e.g. OPA140).

A bigger question is what type of ADC to build with different option for the modulation and the choice of run-down phase or charge measurement on the fly for contineous integration. 
This choice also effects the choice for the reference switches: rel. slow modulation can use current type switching at the integrator side (e.g. like 34401), while fast modulation works better with voltage side switching (like 3446x).
For the modulation it is mainly the choice between
1) classic  2 case modulaton like in 34401,3458,K200x, LD120 or
2) variable PWM like FB (e.g. Solarton, KS3446x).

Usually there is no real need to model the switches in details. The point is keeping the number of switching events constant, so that charge injection only gives an offset that is easy to subtract.
The noise part is relatively easy, though there can be quite some noise sources and in an optimized design several source tend to be comparable.
The stability is mainly a thing of the parts used, especially the resistors.
The linearity part is difficult, as it is about small non ideal effects, beyond the normal linear modelling and is easy to miss parts.

[miro123]

It was quite a while ago since I first started this thread.
I haven’t spent much time on this interesting topic, but I did some simulations and built a small prototype using OPA2140 and OPA209 as slope amplifiers.

I’m still uncertain about the best choice of comparator. I do have good experience with fast latched comparators and programmable hysteresis comparators, but that’s not really the issue here.

My main questions are related to the choice of run-up modulation.
From what I’ve read, most homebrew MS ADC designs use some kind of LD120 PWM modulation, basically a “Ladsburg” type ADC (please correct me if I’m wrong).
I also thought that most HP instruments used that type of modulation, but it turns out this is not true. Looking at the HP Journal 89/4, page 12, Fig. 7:

Pattern 1 and 2 are phase-shift modulated 50% PWMs

Pattern 3 and 4 are center-aligned PWMs

Both approaches are quite easy to generate with the STM32 peripherals. However the coice of patern is stil l not clear for met . Whe to choose patern 1 or 2 and when 3 or 4

So my question is:
👉 What type of run-up modulation do you use?

I’m asking because I want to start developing my first multislope ADC. I would prefer to use the STM32G474, since I know the HRTimer block very well. I think most modulation schemes (including rundown) can be implemented with 0% CPU overhead on that timer and residue ADC. Including the state machine for control rundown

In short: STM32 and mixed-signal processing is my area of knowledge, but I have zero practical experience with building my own multislope ADC.

Comments and suggestions are very welcome.

Greetings,
Miro

[Kleinstein]

The HP journal is not very accurate in the describtion of the ADC. The actual U180 hybrid splits the references in 2 halft with separate switches. There is a chance this is used to get an effective short zero phase by using 1 postive and 1 negative to get "zero" with the same impedance. I am still not sure this is used. The scope pictures I have seen look more like the simple LD120 like system. Another difference is with the fine slopes: there are no larger resistors for the small ref. currents, but a single ladder type DAC with 50 K impedance to nicely match the input path.

For my ADC versions I use the simple LD120 like modulation. In my early (AVR based) version I have testes also other variations.
This was especially a 4 step variant according to US patent 5200752. This version is however not working well. The simple LD120 like method has the nice feature that the number of short pulses of each polarity corresponds to the number of long pulses of the opposite sign. This way, it the short pulses give a slightly different effect as they ideally should have, the effect would still be largely linear. The errors would not add up.

Another point that I have tested is a version with phases of zero ref. current in between. This gives 2 small steps (e.g. postive -> zero -> negative) instead of 1 large step.  Overall I saw little difference and the extra zero complicates things. My current HW solution with an STM32L051 does not support this. As a complication the simple zero phases have a different impedance to the integrator, which is not ideal, as the settling effect is a bit different.

My current plan / idea would be to have still the simple RU pattern, but have the feedback not from the normal slope amplifier, but an extra +1 integrator to make it a 2nd order integrator similar to what is used in many SD ADCs. This way the average integrator voltage would be smaller and less error from DA or idele tones is expected. For SD ADCs it is known that a first order integrator is producing rather strong idle tones.

After the slope amplifier the comparator is no longer that critical. I get away with the µC internal comparator (AVR and STM32L051). This is especially the case if an ADC is used for the final residual charge. For the run-up the comparator is not at all critical and one may even want a little delay (e.g. read the comparator a bit ahead). A slow compartor would mainly add a bit more overshoot and thus a bit more time (maybe 10 µs) spend in the rundown.

For the Integrator I would not use a dual OP-amp. It makes absolute sense to have the 2 OP-amps in the integrator separate to avoid coupling via the supply. So defenitely 2 x OPA140 or an OPA140 and another faster FET input OP-amp for the fast part, as this OP-amp mainly needs to be fast but no need for a low offset or extra low noise.

[miro123]

Thank you for providing valuable insights into MS ADC and for guiding me through this new area. It's good to hear that the classical LD120/Ladsburg ADC is still widely used in both homebrew and commercial products.

Yes, according to the HPJournal, the run-up modulation patterns have small periods where only V in  is active, and also small periods where V
in , Vref+ , and Vref−  are all active. Pattern 1 and 2 use overlap on the edge, while Pattern 3 and 4 have overlap in the middle.

Your idea of using a second-order integrator is interesting. Do you anticipate any stability problems? Do you intend to use a single feedback loop, or multiple feedback loops (from both the first and second integrators)? I assume you'll need to keep the basic run-up phases short, meaning with a low swing but higher frequency. Some idle tones can be filtered by the sync filter if their frequency aligns with a zero in the filter's transfer function

[Kleinstein]

The idle tones are not a thing that can be fixed with filtering. It is more that at certain voltages (e.g. near 50% H/L ratio) persistant patterns can settle and this make INL errors related to switching to add up. Also the average intergrator voltage gets larger and this gives more INL errror from dielectric absorbtion.

The idea for 2nd order FB is to have an extra "integrator" with extra resistor in series to the capacitor to get the sum of 1st and 2nd order integration. This output would only be used for the run-up and the run-down would still use the old path.
One could start with a relativey little of the 2nd order part (large capacitor and resistor) to start from a stable state and than add more of the 2nd order.
A feedback from only the double integration would indeed cause stability issues.
I have not tested myself, but it should be an relatively easy part to add to a new PCB.

[David Hess]

My current plan / idea would be to have still the simple RU pattern, but have the feedback not from the normal slope amplifier, but an extra +1 integrator to make it a 2nd order integrator similar to what is used in many SD ADCs. This way the average integrator voltage would be smaller and less error from DA or idele tones is expected. For SD ADCs it is known that a first order integrator is producing rather strong idle tones.

There should be an input offset error proportional to slew rate in the first operational integrator, which could be corrected by another stage, but I do not know if this error would be significant without calculations, and it would depend on the impedance of the current sources driving it.

[miro123]

The idle tones are not a thing that can be fixed with filtering.

I mean digital filtering. The digital filter input comes at the end of every +Vref and -Vref patern. Still need some simulation to proof that concept will works.

The idea for 2nd order FB is to have an extra "integrator" with extra resistor in series to the capacitor to get the sum of 1st and 2nd order integration. This output would only be used for the run-up and the run-down would still use the old path.

Putting resistor in the second integrator is one way to stabilize the system. Another way is implementing the feed forward path from first integrator. and thirth solution is to use multiple feedback paths. That was my preffered soltion. Most cSD use this approach.

[Kleinstein]

My current plan / idea would be to have still the simple RU pattern, but have the feedback not from the normal slope amplifier, but an extra +1 integrator to make it a 2nd order integrator similar to what is used in many SD ADCs. This way the average integrator voltage would be smaller and less error from DA or idele tones is expected. For SD ADCs it is known that a first order integrator is producing rather strong idle tones.

There should be an input offset error proportional to slew rate in the first operational integrator, which could be corrected by another stage, but I do not know if this error would be significant without calculations, and it would depend on the impedance of the current sources driving it.

The simple 1 OP-amp integrator has an residual voltage (e.g. some 10 mV) at the input. This can be relevant, if the impedance at the integrator input changes (e.g. from run-up to run-down). With extra measures to keep the impedance at the integrator constant (e.g. extra dummy resitors) a simpe 1 amplifier integrator can be OK. This was used with the early MS-ADCs and even the 3458 seems to still have measures to get a constant impedance.
The 2nd OP-amp in the integrator of the 34401 / Keithely 200x and many other modern MS ADCs this 2nd OP amp corrects the residual input voltage, so that only a relatively short pulse (e.g. 0.2 - 2 µs) remains. With this extra measure there is no more absolute need to keep the input impedance constant. The extra pulses tend to only add some fixed offset.
With a 2nd op-amp there is still the choice of using it for the reltively fast correction or only for the really slow part. The 3 OP-amp solution in the HP3458 or ADT6581 is a way to get around the limited speed of the precision OP-amps (e.g. LT1001, OPA177). The OP27 in the 34401 is not ideal with quite some current noise at the input. The 3446x still seem to use the OP27 as fast precision OP-amp, depsite of the extra noise.

The planed 2nd order part for the FB during runup is a different thing: it is there to keep the average voltage at the main integrator output near zero and this way reduce the slow part the dielectric absorbtion. How the feedback is exactly done should not matter much, as the exact pattern does not matter. E.g. noise from the comparator and how the 1st and 2nd order part are mixed during run-up does not matter. RU is mainly about keeping the integrator within bounds and correct accounting for the charge.

[miro123]

If you goal is to keep the dc close to 0Volts, you can still you you old hardware with signle integrator.
1. You know the moment when you start next segment t=0
2. You can capture the monent when slope crosses 0V - output from comparator t=Tcaptiure
3. You know how long is one LD120 segment - e.g. 100KHz T2= 1use

If  Tcapture > T2/2 -> you are more on the negative side
If  Tcapture = T2 /2-> you are exactly on the middle
If  Tcapture < T2 /2-> you are more on the negative side

Taking decision on digital domain has many advantages
1. Higher performance - even per cycle you know where you are related to 0V -
2. Flexibility - easy to change algorthim and tune the integrator behavior - Fc and Gain - For simple RC integrator/LPF you can go with PI controller

One condition - requirement for comparator are tighter.

BTW: which opamps are used  3446x integrator. are there some scope pictures of integrator sweeps on MS IV ADCs

[Kleinstein]

Using the timing and kind of do extra compensation in software is a nice idea. It still is some effort with not too much time to react.
With external sychronization to a clock in the 10-20 MHz range it gets complicated when the µC runs on a different higher clock speed. It could be done, but would be an extra step for the phase from the PLL.
The comparator should still not be critical.  The point is to avoid the simple one sided patterns that can give quite high average integrator voltage (e.g. reaching negative just barely every time). So the µC internal comparator or a LM393 / LM311 (is convenient with level shift at the output) should be good enough. Comparator noise does not matter during RU and a few 100 ns late would not make a big difference (mainly take away from time for computation).

There is a leaked schematics of the 34410. There they have an OP27 as precision OP-amp and JFET Source follower and AD829 for the output / fast part.
The rather small capacitor (47 pF) suggests a very high modulation frequency likely in the 1.5 - 2 MHz range.
This is good for very fast conversions (e.g. > 500 kSPS for digital RMS for AC), but not ideal for precision and low noise with slow conversions.
AFAIK the ADC part in the 3446x has not changed much. AFAIR from photos they did however change the fast OP-amp to some Ti type I could not identify.

[iMo]

..There is a leaked schematics of the 34410. There they have an OP27 as precision OP-amp and JFET Source follower and AD829 for the output / fast part.
The rather small capacitor (47 pF) suggests a very high modulation frequency likely in the 1.5 - 2 MHz range.
This is good for very fast conversions (e.g. > 500 kSPS for digital RMS for AC), but not ideal for precision and low noise with slow conversions..

How their ADC actually works? They have there the integrator (op27+ad829), which ends up in two ADCs (chips) - 11bit "fine" clocked with FINE_CLK, and "coarse" clocked with COARSE_CLK. No comparator or a fb to the fpga  - do they use the ADCs for some on-the-fly interpolation? Does not look as a MS..
The ADC has a hard wired input DAM_OUT (via the 20k) which is a PWM (synced to 106.25MHz master clock, with +/-9Vref 50ohm imp. levels) and an DC_OUT input (via the 50k and fet switch)..
The TL071 there somehow manipulates the COARSE ref point..

[Kleinstein]

AFAIK the MS4 uses the coarse ADC for feedback in the RU part and not just 2 patterns, but a more contineous PWM like feedback. Somehow the fine ADC gets a reading relatively close to the zero crossing and this is than used for additinal resolution. The operation also seams to be more like a SD ADC, with non stop integration and using more than just a single start and stop. It makes it a quite complex ADC that seems to work well at higher speed. The performance for lower speeds like 1PLC is however not that great, though still quite a bit better than the 34401.

[David Hess]

If you goal is to keep the dc close to 0Volts, you can still you you old hardware with signle integrator.
1. You know the moment when you start next segment t=0
2. You can capture the monent when slope crosses 0V - output from comparator t=Tcaptiure
3. You know how long is one LD120 segment - e.g. 100KHz T2= 1use

If  Tcapture > T2/2 -> you are more on the negative side
If  Tcapture > T2 /2-> you are exactly on the middle
If  Tcapture > T2 /2-> you are more on the negative side

Taking decision on digital domain has many advantages
1. Higher performance - even per cycle you know where you are related to 0V -
2. Flexibility - easy to change algorthim and tune the integrator behavior - Fc and Gain - For simple RC integrator/LPF you can go with PI controller

One condition - requirement for comparator are tighter.

BTW: which opamps are used  3446x integrator. are there some scope pictures of integrator sweeps on MS IV ADCs

The real behavior of the operational integrator is more complicated.  The input offset voltage varies proportionally to the slew rate by a factor depending on DC open loop gain, which itself varies with temperature and other things.  There is also a dynamic component to the input offset voltage which depends on gain-bandwidth product; the operational integrator is always a little bit "late", which becomes more important when the input current changes quickly.  I have never observed it, but there should also be a settling time component.  It is only because of the high resolution of the ADC in this case, parts per million and better, and reduction of other errors like dielectric absorption and charge injection, (1) that errors from the operational integrator become significant.

Higher speed integrators, like in function generators, take a different form because operational integrators are a worst case situation for operational amplifiers where unity gain stability and high gain-bandwidth product conflict.

(1) The Siliconix LD120 design is notable for solving, or at least moderating, the charge injection and dielectric absorption problems, but suffered from poor linearity from the uncorrected common mode rejection of the input buffer, which was partially corrected with the LD122 by using an external higher performance buffer.  Unfortunately at the time, suitable precision JFET operational amplifiers also had limited common mode rejection, but they were barely good enough.

[miro123]

[
How their ADC actually works? They have there the integrator (op27+ad829), which ends up in two ADCs (chips) - 11bit "fine" clocked with FINE_CLK, and "coarse" clocked with COARSE_CLK. No comparator or a fb to the fpga  - do they use the ADCs for some on-the-fly interpolation? Does not look as a MS..
The ADC has a hard wired input DAM_OUT (via the 20k) which is a PWM (synced to 106.25MHz master clock, with +/-9Vref 50ohm imp. levels) and an DC_OUT input (via the 50k and fet switch)..

Some data over MS 4 is available here, Tip look at the text section too - there is long list with source info

[jgustavoam]

My DVM project using the Raspberry Pico is still under development, but I have already achieved excellent results such as measuring positive voltages from 0 to 2.500V with good accuracy and stability.

Using an old technology, but still used in Voltmeters today - Dual slope ADC. The counter/timer uses the RP2040 processor clock frequency of 200 MHz. Therefore, the resolution is 5 nanoseconds. This allows for greater precision and resolution for the DVM.

The circuit was assembled with the Raspberry Pico - RP2040. But it can be modified for the Raspberry Pico 2 including WIFI and Bluetooth - Raspberry Pico W.

Currently the DVM measures positive voltages, but it could be implemented to measure negative voltages as well (in future)

To vary the range of voltages to be measured, voltage dividers with precision resistors can be implemented at input of the DVM. The same circuit is used in modern voltmeters.

Digital Voltmeter with 4 ½ digits - Raspberry Pico
https://forums.raspberrypi.com/viewtopic.php?t=391945

Link Github:
https://github.com/Gustavomurta/tinyGo_my_experiments/tree/main/Raspberry_Pico/DVM_4halfDigits

Using Tinygo - easy, fast and amazing language to control microcontrollers.

Voltage at input : 1.025V

Calibration: 131000 // Auto Zero Period: 41968 ticks // Voltage Auto Zero: 0.031 V # VIN Period: 1365937 ticks // VIN Voltage: 1.025 V
Calibration: 131000 // Auto Zero Period: 41953 ticks // Voltage Auto Zero: 0.031 V # VIN Period: 1365973 ticks // VIN Voltage: 1.025 V
Calibration: 131000 // Auto Zero Period: 41878 ticks // Voltage Auto Zero: 0.031 V # VIN Period: 1366006 ticks // VIN Voltage: 1.025 V
Calibration: 131000 // Auto Zero Period: 41862 ticks // Voltage Auto Zero: 0.031 V # VIN Period: 1365980 ticks // VIN Voltage: 1.025 V
Calibration: 131000 // Auto Zero Period: 41906 ticks // Voltage Auto Zero: 0.031 V # VIN Period: 1365927 ticks // VIN Voltage: 1.025 V
Calibration: 131000 // Auto Zero Period: 41885 ticks // Voltage Auto Zero: 0.031 V # VIN Period: 1365882 ticks // VIN Voltage: 1.025 V
Calibration: 131000 // Auto Zero Period: 41719 ticks // Voltage Auto Zero: 0.031 V # VIN Period: 1365938 ticks // VIN Voltage: 1.025 V
Calibration: 131000 // Auto Zero Period: 41706 ticks // Voltage Auto Zero: 0.031 V # VIN Period: 1365915 ticks // VIN Voltage: 1.025 V
Calibration: 131000 // Auto Zero Period: 41741 ticks // Voltage Auto Zero: 0.031 V # VIN Period: 1365878 ticks // VIN Voltage: 1.025 V
Calibration: 131000 // Auto Zero Period: 41398 ticks // Voltage Auto Zero: 0.031 V # VIN Period: 1365922 ticks // VIN Voltage: 1.025 V
Calibration: 131000 // Auto Zero Period: 41703 ticks // Voltage Auto Zero: 0.031 V # VIN Period: 1365896 ticks // VIN Voltage: 1.025 V
Calibration: 131000 // Auto Zero Period: 41824 ticks // Voltage Auto Zero: 0.031 V # VIN Period: 1365890 ticks // VIN Voltage: 1.025 V
Calibration: 131000 // Auto Zero Period: 41825 ticks // Voltage Auto Zero: 0.031 V # VIN Period: 1365843 ticks // VIN Voltage: 1.025 V
Calibration: 131000 // Auto Zero Period: 41795 ticks // Voltage Auto Zero: 0.031 V # VIN Period: 1365878 ticks // VIN Voltage: 1.025 V
Calibration: 131000 // Auto Zero Period: 41732 ticks // Voltage Auto Zero: 0.031 V # VIN Period: 1365985 ticks // VIN Voltage: 1.025 V


Since I increased the integration time to 16.666 ms, now the number of bits has increased! Now I can say that it is more than 21 bits

Due to the stability of the measurements, I was able to increase the sampling rate to 10 measurements per second.

60Hz period = 1/60 = 16,666,666 (uint32) time in nanoseconds.
Ticks = 16,666,666 / 5 = 3,333,333 (uint32) each tick is 5 ns
VREF = 2.500V
LSB Voltage = 2.500 V / 3,333,333 = 7.5e-7 ( least significant bit: 750 nano Volts!)

2 ^ 20 bits = 1,048,576
2 ^ 21 bits = 2,097,152
2 ^ 22 bits = 4.194.304
Code: Select all

Dual Slope ADC RP2040 V11
AC mains period: 16666666 ns
LSB Voltage: 0.000000750 V
CPU Frequency: 200000000 Hz
Nanoseconds per tick: 5

[Kleinstein]

The OP07 shown as OP-amp for the integrator and used as comparator is not a good choice. It is a bit slow and the input bias current adds offset.
An actual comparator like LM393 should work better as comparator as the slow OP07. They have a common collector output and thus would not need the extra transistor at the output. For the OP07 a +-3.3 V supply is border-line low.
For the integrator better choice would be something like OPA202 or OPA1641, OPA141. When looking for a DIP part an OPA134 would be a good choice.
For not so high a resolution even the classic TL072 ot TLC272 would be an option, especially with not so long integration at a time and AZ loop.

For the ADC the theoretical resolution or quantization steps are only one part that limits the resolution. The more difficult part is the noise, especially when it comes to higher resolution. It still makes sense to have the quantization steps well smaller than the noise limit, if it comes with little effort. This especially the case with multi-slop designs, that have it easy to very small quantization steps. The real limit to resolution is more the noise.

The reset part looks odd, using the enable pin of the switch chip.
With a µC to control the ADC one could do the zeroing in a digital AZ loop. So the ADC alternated between reading the actual input voltage and a zero reading. The result is than the difference of the 2 readings. The AZ loop limits how low frequencies are relevant and can thus limit the 1/f noise effect.
So far I don't see switching of the input signal.

[PCB.Wiz]

Using an old technology, but still used in Voltmeters today - Dual slope ADC.

If you are chasing resolution, some comments:

 Common Dual Slope design has a single shared resistor (so R8 and R9 merge and move to 4051 output), which eliminates resistor drift and matching issues, as the same resistor is used for charge and discharge.
 The LM336 is rather 'old and ordinary', if you are taking the trouble to make a good ADC, a better ref is well worth it.
The LM336 is spec'd to about one part in 415 worst case or typical one part in 1400 over temperature, so that's just over 10 bits.
 

eg a REF3425 is 0.05% and typ 2.5ppm/°C max 6 ppm/°C

[jgustavoam]

Thank you for your interest, Kleinsten and PCB.Wiz.
Thanks for the tips.

Some explanations:

The OP07 operational amplifier was chosen because it's easy to obtain (I am Brazilian and I live in Brazil), it's cheap, and it's performing very well in this project.
I have some OP177s here, but I haven't tested them yet.

https://www.analog.com/media/en/technical-documentation/data-sheets/op07.pdf
OP07C = Low VOS: 60 μV (typical)
Closed-Loop Bandwidth : 0.6 MHz (typical)

https://www.analog.com/media/en/technical-documentation/data-sheets/op177.pdf


The LM393 seems to have a higher offset voltage than OP07. Then I can test the LM393 in my project.
Low input offset: 370 uV (typical) LM393B
Faster response time of 1µsec
https://www.ti.com/lit/ds/symlink/lm393.pdf?

With a µC to control the ADC one could do the zeroing in a digital AZ loop. So the ADC alternated between reading the actual input voltage and a zero reading. The result is than the difference of the 2 readings. The AZ loop limits how low frequencies are relevant and can thus limit the 1/f noise effect.
So far I don't see switching of the input signal.

I haven't had time to edit the entire project theory yet because it's so extensive. I'll get it done.
The Auto Zero process adds precision to my project. This allows me to achieve linearity during the 0 to 2.500V range.
Regarding the rate of 10 measurements per second, it's easier to check with an oscilloscope or logic analyzer. I'll arrange to share these images as soon as possible.

Common Dual Slope design has a single shared resistor (so R8 and R9 merge and move to 4051 output), which eliminates resistor drift and matching issues, as the same resistor is used for charge and discharge.
 The LM336 is rather 'old and ordinary', if you are taking the trouble to make a good ADC, a better ref is well worth it.

I had already considered removing resistors R8, R9, and R11 and inserting just one resistor at the output of the 74HC4051 U1. I ran some tests, and since they were failing, I gave up. I may try again.
Regarding VREF with LM336 2.5V, it was one of the voltage references I had here. Very stable, but I'll test with others.

I've already researched some voltage references, including REF 3425. My problem is that here in Brazil there aren't some and the shipping costs for imports are absurd!

OBS: My old Fluke 70 III uses a LM385Z 1.2V as a voltage reference.

[Kleinstein]

The offset voltage of the comparator usually does not matter. This corrected with a zero reading as well. It is more about not too much noise and enough speed. The speed may be less relevant when looking only at one sign. It can be an issue around 0, as the required response times get lower and lower.

A dual slope for both signs can add quite some complications. One may need to adjust the steps around zero, not to end up with +0 V and -0 V or a missing 0 reading. There are still many different ways to implenet it:
1) a 2nd inverted reference
2) add some shift to ground and have input zero at the middle of the ADC one sided range.
3) change the signal polarity before the ADC

A main point of the dual slope is indeed using the same resistor for run-up an run-down. It is the main advantage over a multi-slope version, that could get less noise, more speed and better linearity (less effect of DA).

[jgustavoam]

The offset voltage of the comparator usually does not matter. This corrected with a zero reading as well. It is more about not too much noise and enough speed. The speed may be less relevant when looking only at one sign. It can be an issue around 0, as the required response times get lower and lower.

A dual slope for both signs can add quite some complications. One may need to adjust the steps around zero, not to end up with +0 V and -0 V or a missing 0 reading. There are still many different ways to implenet it:
1) a 2nd inverted reference
2) add some shift to ground and have input zero at the middle of the ADC one sided range.
3) change the signal polarity before the ADC

A main point of the dual slope is indeed using the same resistor for run-up an run-down. It is the main advantage over a multi-slope version, that could get less noise, more speed and better linearity (less effect of DA).

Thanks for the tips.

The offset doesn't really matter, as it is subtracted during the AutoZero process.

Code: [Select]

vrefPeriod = startPeriod - endPeriod // period of VREF integration

fmt.Printf("Calibration: %d // ", calibrate)
fmt.Printf("Auto Zero Period: %d ticks // ", autoZeroPeriod)
voltageZero = float32(autoZeroPeriod) * voltageLSB // Auto zero voltage calculation 7.5e-7
fmt.Printf("Voltage Auto Zero: %.3f V # ", voltageZero)

vinPeriod = (vrefPeriod - autoZeroPeriod) // period of VIN integration

fmt.Printf("VIN Period: %d ticks // ", vinPeriod)
voltage = float32(vinPeriod) * voltageLSB // VIN voltage calculation 7.5e-7
fmt.Printf("VIN Voltage: %.3f V\n", voltage)

To implement negative voltage measurement:

- I'll invert the reference voltage - that seems simple to me.
- Regarding the -15mV V Offset, it seems I can use it. But I haven't tested it yet. This V Offset is essential for the Dual-Slope ADC to work, to avoid oscillations in the circuit.
- Regarding polarity identification, I think I can use the output comparator. But I haven't tested it yet.

[Kleinstein]

One can use the output compartor to look at the sign of the signal. However this conflicts with the 15 mV offset at the non-inverting input. One would kind of want to invert that offset also depending on the signal sign. As is the ADC would work from something like -10 mV to maybe -2.5 V (more limited by the buffer at the input).
With an inverted reference it would than work from maybe -2.5 V to -20 mV. So there is sine dead zone between the 2 cases.

The offset is not really needed against oscillation, it is more about avoiding a super short run-down of only a few µC cycles, that can also cause some DNL error around that point.

[miro123]

I have just looked at Fluke patent US 5,321,403.
It used interesting run up modulation with cycles when two Vref are on or two are off. I mean +Vref and -Vref
It also describes the calibration of switch own injected and cross-injected energy calibration.
It is interesting to see how they do two type of flat section modulation to cancel out the cross coupled charge injection
Does somebody try it such approach?

[David Hess]

I have just looked at Fluke patent US 5,321,403.
It used interesting run up modulation with cycles when two Vref are on or two are off. I mean +Vref and -Vref
It also describes the calibration of switch own injected and cross-injected energy calibration.
It is interesting to see how they do two type of flat section modulation to cancel out the cross coupled charge injection
Does somebody try it such approach?

That sounds like what Siliconix did in their integrating ADC chipsets.  Errors from charge injection can be cancelled out by balancing the number of switch events.

[Kleinstein]

I think the main idea is to reduce the jump from switching from +ref to -ref in one step. So they split the step in 2 small ones. This can be somewhat relevant of the integrator uses a relatively small integration capacitor. In this case the transisent voltage at the integrator input can get relatively large and may get close to the linearity limits (some 20 mV) for a BJT based OP-amp (e.g. OPA177 or OP27 for the precision part). With only FET based OP-amps at the intergrator the limits would be higher and modern OP-amps also tend to be faster and thus lower transients.

I have tried an extra zero phase in between, however in both cases with the both references off. It works, but I saw no difference in the performance (noise and hard INL test) to switching both reference at the same time. It is the choice of 2 small steps versus 1 double size. The 2 steps can have an issue due to the change in the intergator input resistance. This could make it a bit sensitive to a loading effect to the integrator output, that can effect the OP-amps GBW and this way the transients. This may than cause some INL issues, especially with using both versions as in the patent.

The 3458 ADc goes one step further: the references are split in 2 equal size parts so one has 2 x pos ref. and 2 x neg ref. A combination of 1x pos and 1 x neg gives a zero phase with the same impedance. However the description in the HP journal does not include the spilt references and the observed integrator waveform seem shows no or only a super short (like 50 ns) neutral phase.

The 2 seprate steps should have a slight advantage with clock jitter, but this is only the clock part.
Using a constant switching rate is definitely a good idea. Comparing different switching rates showed some extra drift.