Is there any public data, or community insight on best practices to prevent leakage from low-current traces?
For pcb features that involve exposed copper such as component pads and vias, the area can be surrounded with a driven guard. This technique reduces pcb surface conduction especially from deposited oil and contaminates and under varying environmental conditions/humidity, by keeping voltage potentials the same.
But there are also choices about how to route traces. For example a low current trace could be -
- sandwiched between fr4 laminates, versus
- routed on the pcb surface and covered by solder mask
These design choices affect board complexity and cost. So it would be good to know what the relative benefit is/ or if there is any benefit.