Low noise chopper and DIY nV meter

[CurtisSeizert]

A combination of a fixed bias (e.g. leakage from FETs and diodes) and a net charge injection from the modulator sounds resonabel. The slope in the two curves with bias vs DAC value is close to the 2:1 frequency ratio.  A DAC value of ~ 490 to gets zero bias with 3600 Hz. At 7200 this would 2 fold compensate the static bias.  This would suggest some +160 pA of static bias.

The diodes and JFE2140 should not give that much leakage. So chance are it could be from the modulator FETs, that are made for RF performance and not so much for low leakage.

I tested a couple samples of the PE4140s for gate leakage before designing the board around them. I got <100fA at -3V. They have minimal ESD protection (The HBM rating is 100 V), so there aren't protection structures to give additional leakage. I do need to just test the static bias by turning the modulator off still, but the reason why I don't think it is as simple as being able to directly compare the DAC low codes between frequencies is that if one repeats your analysis for more frequencies, the result for static bias is different each time. The zero-bias code change gets smaller each time you halve the frequency, until it remains essentially constant below 900 Hz. A code of 900 for both 900 Hz and 225 Hz gives an absolute value for bias current of <1 pA. There may be some frequency dependence for turn off behavior since the body is not tied to gate or source, so during the off cycle it is floating. I don't know definitively, but from what I can piece together from patents, the PE4140 is a 25 nm film-thickness FDSOI FET, and kink effects have been observed in such devices (https://www.sciencedirect.com/science/article/abs/pii/S0038110117308651), so perhaps that is a factor here, but that is just speculation.

There is also a significant effect with modulator deadtime, with longer deadtimes at the same modulator code making the charge injected per cycle increasingly negative. The correspondence is not linear, but with the limited range I tested, from 78-109 ns, the value was around 1-2 fC/ns. The noise performance is best at short dead times, but the effect size is small. It's only about a 3% reduction going from 93 ns to 31 ns. I did this with 0R source resistance, so I don't know about current noise. There is no impact whatsoever with demodulator deadtimes over the range I tested. If you plot the charge injected per cycle against the modulator low level code at all frequencies and deadtimes I have looked at, the value is -70 to -78 aC/LSB. I would need to randomize the order of experiments before I could make any statements about what impacts that. Also, the zero bias code at a given frequency is temperature dependent, which makes sense as the modulator gate threshold voltage is temperature dependent.

I have not been collecting temperature data because I have had some issues with getting the linked list DMA thing to handle the I2C reads, so I have been calling blocking functions to get the temperature data from the sensors, and this does not work well at high modulator frequencies because the SPI reads from the AD4030 have to be blocking (software NCS given the octoSPI woes), and it's much faster to poll for SPI transfer completion and pull the NCS high than it is to do the same thing with interrupts (680 ns vs 799 ns NCS low time).

[CurtisSeizert]

I have finally hooked up the NVM to start measuring some external voltages, and I can tell that it will be a challenge to maintain the performance of the internal short. The change in offset between shorting the inputs internally and externally is not much. With the modulator frequency at 1800 Hz and the ADC switches at 200 Hz, I saw 37 nV and 45 nV respectively for internal vs. external. There are Pomona low thermal EMF binding posts on the front panel, and I was using a piece of unfluxed solder wick as the short. However, to get decent readings, those binding posts need to be covered from drafts. The susceptibility to mains-frequency noise is much greater, unsurprisingly, though the situation with a short is not too dire when everything is closed up. I found that the powerline noise would just alias back to lower and lower frequencies when averaging blocks of samples if I used frequencies that were not a multiple of 60 Hz. I tried 315 and 1770 Hz, and they were a mess. With 1770 Hz, there was a peak at around 350 mHz.

Using a 49k95/50R divider, I measured some voltages from my power supply, and the issue was much worse. For some reason I cannot explain, the gain on both channels is 25% lower than what it should be from the schematic (I am using values of 2002 and 202 for the high and low gain settings). The issue does not seem to be with the chopper stage - on the high gain setting (1001x), I measured a gain of 1009 for the front end and 2020 at the ADC inputs. From the limited work I have done to diagnose the issue, I know it is unrelated to the sample rate of the ADC, as I get the same numbers with 500 kSPS and 2MSPS.

The additional inductance from putting a short at the front panel definitely causes some gain peaking for both settings. I think it would probably be best to slow them both down a bit by increasing the integrator capacitance from 47 to 68 pF and same with the feedback capacitance. As I was investigating this and running some simulations, I think I had conflated SPICE not converging with instability on the 101x gain setting. The pole-zero network in the feedback for that doesn't seem to be crucial (I took it out on the board too). The point where open loop goes >0 dB with positive feedback is at >100 MHz, and this does not seem like a real issue with the parts I am using because the diff amp and the ADA4625-1 just don't have that kind of bandwidth. The phase margin at 40 dB closed loop gain does leave a bit to be desired, but increasing the value of the caps as above should work. I think this is important because the increased noise from the low gain setting relative to the analog out is almost certainly related to aliasing, and having the gain go to 60 dB at higher frequencies was probably not helping. My general sense is that you need to take antialiasing very seriously with oversampled SAR ADCs at this kind of resolution. Clearly, it is not just the SAR ADC though, which is apparent from the low frequency spectrum with a 315 Hz modulator clock.

Speaking of aliasing, I looked at the noise from the PSU, and it is definitely a target for improvement. I think the +8V5 rail noise is making it to the analog outputs, but this is still at the level of a strong suspicion, and I haven't powered all the rails with linear supplies to confirm this. The noise spectrum of the +8V5 rail has a lot of lower frequency stuff (~10 kHz and harmonics, switching at 2 MHz). I took a spectrum of all the rails (attached) using a test board with some resistive loads. I know from some previous experiments that the noise spectrum of the +8V5 rail gets better with heavier loads, so I think that it is a combination of the controller going into burst mode and ring-off when the switch goes high impedance. I have made changes to the schematics for the next revision and have added another Cuk (not inverting) to power the ADR1399 heater based on Andreas's notes. It may be better to actually use the same topology for the +8V5 rail, as I was able to get very good efficiency in simulations while staying in CCM at light loads (of course, this requires very large inductors). I think that staying in CCM is crucial for this application because of the noise sensitivity, and the radiated emissions from ring off could easily alias into the pass band. I don't see a lot of high frequency content in the spectra for the primary rails supplied by the SMPS board, but I haven't checked around with an E field probe to see if there are radiated emissions coming from high dv/dt transients.

Ultimately, I don't know that it will be optional to synchronize the modulator clocks with the mains to get good performance here. I have an isolated input I can use for such a clocking signal, and I have designed a board to drive it. I am still learning about DSP, but from what I can gather, FIR filters, like a block averaging filter, will generally be susceptible to aliasing unless the spurious signal lands in a null. I feel like it would be helpful to use an IIR filter for the offsets to mimic what I did with the proof of concept version with Rs and Cs to reduce the susceptibility to noise, but I will have to test this. I have attached some spectra I took of the analog out and power supply. The modulator clock was 1800 Hz unless otherwise specified.

[Kleinstein]

For the curves with the external short one can see the expected extra low frequency noise. It is however not so clear how much of this may be coming from the scope. To really judge on the low frequency / longer time scale performance I would prefer to look at an Allan deviation plot from data taken via the ADC.

I think much of the extra frequency signals at higher frequency and maybe also some of the lower frequency ones could be from the scope sampling the signal all the time, including the switching spike of the modulator.

For the digital filtering the block averaging is best for white noise, but has the side lobes at higher frequencies. A more classic FIR filter can suppress the side lobes better, but at the cost of more noise bandwidth and thus more noise from close by. It would still help to suppress interfrerence from some higher frequency. I would prefer a filter still relatively close to the block averaging, with only somewhat smooth start and stop of the aperture.
I don't think the offset correction part should be that critical. In first approximation the offset does not contribute to a signal / noise below half the modulation frequency. It is more that the offset of the JFET amplifier can effect the current spike at the input and the switching transisents.

I agree that it can make sense to slow down the amplifier a little more. This could help with stability for the gain 100 (e.g. reduce ringing after the modulation steps). For the really high frequencies approaching 100 MHz the models for the transistors and OP-amp may not longer be accurate and parasitics can come in. A point that can change things is also the capacitance of the gain setting switches.

With a SAR ADC aliasing can be serious, but most of this should be handled with the ADC driver and filter there.
The other from of aliasing can be from the modulator.

[CurtisSeizert]

I am focusing on trying to get the ADC readings to make sense right now, and once I have done that, I'll take a long capture and make an Allan plot. I have generally found it counterproductive to troubleshoot with flawed analytical methods because it can become confusing to remember which conclusions one has drawn have an asterisk next to them. That said, the ADC data at high gain match the analog out quite well for small-signal stuff, so I have a couple spectra that show the increase in noise going from internal short to external short with covered terminals to external short with exposed terminals.

The reason I think aliasing is a big deal is because an integrating ADC (HP 3458A) shows an NSD that is 40% lower than the internal SAR ADC on the low gain setting. I am sure there are possible scenarios where that is not aliasing, but I would think that aliasing is the first suspect. That may help contextualize the motivation for getting those FFTs of the analog out from the scope - I wanted (among other things) to understand what spectral components could be the the root cause of this. In general, the fundamental at 8 kHz and its associated harmonics stay at the same level for both gain settings, and the peaks at the modulator frequency and its harmonics rise above the white noise more at the lower gain (compare the two attached spectra with dark backgrounds). I would guess that the increase in white noise density with the external short is, at least partly, due to the broadband noise aliasing back into the passband amplified by the gain peaking associated with the additional source inductance.

I cannot rule out aliasing as a result of the odd ADC readings as one of the input switch settings gives readings that are too low (not closer to zero - they are the larger absolute value with negative input voltages) and the other gives readings that are too high. For example, When I should be getting about 2.01 V, I am seeing codes that equate to 2.34 V and 0.67 V. Everything on the analog side looks fine, so I think this is probably a code issue (or a bad part issue). I mention this because if this is a difference in absolute values for the weights of each phase of the cycle, then spurious signals could also fold back over 1/2 f_ADCSW, though to a lesser extent than if one of the weights were zero.

[CurtisSeizert]

I fixed the weird ADC voltage thing. The SPI bus won't do 64 MHz unless you go to the highest power scaling setting, and bits were being shifted right by one position. I don't know how that worked with negative numbers, but anyways I am getting 1.0038 mV for something that my 34465A says is 0.9996 mV and same story with the polarity reversed. It is exciting when you put this much work into something and finally get it to the point where it can do something nominally useful.

[macaba]

Hi Curtis, i haven’t had the chance to keep up with this thread & hoping to find some time to read it however I get the impression you might have excess ADC noise? In which case, perhaps change your 2x input R to 4.7 ohm, change 2x CM caps to 100pF and add a differential cap of 10nF. This is a practical tip from my workbench, not theory.

Edit: if you short the inputs of your FDA to 0V (inputs of U36) and measure the NSD (scaling ADC values with reference voltage of 5V) then I would expect OPA+FDA+ADC NSD in the range of 20-30nV/rHz (ADC alone with short directly at inputs is about 18nV/rHz). If more then try the filter modification I suggested above for sure.

[CurtisSeizert]

Hi Curtis, i haven’t had the chance to keep up with this thread & hoping to find some time to read it however I get the impression you might have excess ADC noise? In which case, perhaps change your 2x input R to 4.7 ohm, change 2x CM caps to 100pF and add a differential cap of 10nF. This is a practical tip from my workbench, not theory.

Edit: if you short the inputs of your FDA to 0V (inputs of U36) and measure the NSD (scaling ADC values with reference voltage of 5V) then I would expect OPA+FDA+ADC NSD in the range of 20-30nV/rHz (ADC alone with short directly at inputs is about 18nV/rHz). If more then try the filter modification I suggested above for sure.

I am interested to know if my descent into madness comes through as you read the thread. Also, I appreciate the practical tip. I may try that out because the input filter does not have the bandwidth to support 2 MSPS operation (68R/2.7nF), and it should be beneficial to operate at a higher sampling rate to help with aliasing. Every time I rework this board I hope it will be the last time. The five or ten minutes of actual reworking turns into two hours or so between disassembly, popping off all the shielding covers, preheating, cleaning, baking, and reassembly.

I can actually just interrupt normal acquisition in a serial terminal and switch the measurement to have both ADC input switches connected to Vcm or the output of the chopper stage. I have done some experiments where I do that, and the results are the same regardless of which one I am measuring, but I will need to repeat those with the code fixes I have made. With the inputs of the TMUX4053 shorted (U32 if you have the schematic handy), by my reckoning, I should see about 31 nV/rtHz (28 from the diff amp block at gain of 2, and 13 from the AD4030 (it is a factor of sqrt(2) quieter than the AD4630). I actually see 58 nV/rtHz at 2 MSPS, going an order of magnitude higher at 500 kSPS. Those are provisional values, so I will repeat the experiment before I make any changes to the board.

I hooked up the bench supply to power the board rather than the SMPS daughterboard, and I found that the 8 kHz and harmonics that I saw before were indeed due to the SMPS as they are absent without it. I've included both spectra here. I still see some peaking in the response with the added inductance of the protection circuitry with the integrator and feedback caps changed from 47pF to 68 pF (see the NVM B External short spectrum). I may try to fix this by increasing the value of those caps even more. It isn't really clear to me that this is problematic with respect to ADC aliasing because there isn't really any difference in NSD when I increase the sample rate.

I have done some very preliminary linearity measurements, and while I have found the analog out to be linear to within experimental uncertainty, there are certain points where the ADC readings deviate considerably from expectation, often very near points that read fine. That makes me think it is a data processing issue. For example, there is a 1% decrease in gain going from 815 uV, which reads as expected, to 810 uV, which does not. My source is a 200k/20R divider using some discrete BMF through hole resistors I had lying around attached to various things that I can drive from a battery (or a battery itself), so I am stuck with measuring certain discrete voltages at the moment.

The ADR1399 board is up and at least partly running. The Cuk won't start up with the large initial current demands of the heater (it looks like about 140 mA), so I need to power the negative rail externally for the first ten seconds or so. The current draw at 15 V increases about 50% relative to the LTC6655, from 39 mA to 60 mA, and the noise performance on the high gain setting seems to be worse. I don't think this is solely attributable to heat diffusion, as the increase is visible up to about 10 Hz, which is probably too fast for thermal effects in a closed case with the shields on. The offset voltage is marginally higher than before, which probably is thermal. The increased heat from the reference accentuates the imbalances in dissipation around the input switch that are present in the LTC6655 board.

[Kleinstein]

The inductor at the input can pick up magnetic interference. Some of the noise in the 200 kHz range may come from a SMPS or AM radio.
So it may be more than just the added inductance. The added inductance could effect the settling after the modulator switching.

[macaba]

Curtis,

I tend to think that with any kind of ultra precision instrumentation project, a descent into madness is inevitable and perhaps even desirable! A certain kind of manic ultra-focus is sometimes needed at this level as a lone developer.

With the inputs of the TMUX4053 shorted (U32 if you have the schematic handy), by my reckoning, I should see about 31 nV/rtHz (28 from the diff amp block at gain of 2, and 13 from the AD4030 (it is a factor of sqrt(2) quieter than the AD4630). I actually see 58 nV/rtHz at 2 MSPS, going an order of magnitude higher at 500 kSPS.

Your reckoning seems about right to me, and your 58nV/rHz (assuming no calculation error) is further proof - I also saw an approximate doubling/tripling of noise until I fitted the correct charge kickback filter values. It seems the precharge circuitry on these ADCs simply reduce, not eliminate, the issue.

[CurtisSeizert]

Curtis,

I tend to think that with any kind of ultra precision instrumentation project, a descent into madness is inevitable and perhaps even desirable! A certain kind of manic ultra-focus is sometimes needed at this level as a lone developer.

With the inputs of the TMUX4053 shorted (U32 if you have the schematic handy), by my reckoning, I should see about 31 nV/rtHz (28 from the diff amp block at gain of 2, and 13 from the AD4030 (it is a factor of sqrt(2) quieter than the AD4630). I actually see 58 nV/rtHz at 2 MSPS, going an order of magnitude higher at 500 kSPS.

Your reckoning seems about right to me, and your 58nV/rHz (assuming no calculation error) is further proof - I also saw an approximate doubling/tripling of noise until I fitted the correct charge kickback filter values. It seems the precharge circuitry on these ADCs simply reduce, not eliminate, the issue.

Yeah, I had been putting in 12 hours a day in February, but I have slowed down a bit now. Most of my coding experience, and about 95% of my C coding experience has been writing high performance algorithms in CUDA, and that was about 8 years ago. Incidentally, that subtly gave me an aversion to flow control because branching statements are really bad when you're trying to keep blocks of threads coherent. Anyways, here is the data for ADC noise. For the LTC6655 board I fitted an ADA4805-2 as the ADC driver rather than a 4807 because it's a better fit for 500kSPS, which I had planned on using. As I mentioned, the RC filters are 68R/2.7nF, so at sample rates significantly greater than 500kSPS, the input has not fully settled (the bandwidth is ~850 kHz). According to ADI's tool, we're talking about a handul of ppms at 2MSPS, so presumably we can trust a couple digits of precision for these results.

500k: 381.0 nV/rtHz
1M: 348.4 nV/rtHz
2M: 42.8 nV/rtHz

The measurement conditions were a bit different, and I was relying on memory for the value at 2 MSPS, so both of those might be the reason for the discrepancy. The 2 MSPS value is repeatable to beyond the precision I gave, but the others are not. Interestingly, this does not manifest in an increase in LF noise in the spectrum as the 1MSPS and 500kSPS are both flat. With 2 MSPS, I do start to see some 1/f noise from the driver at LF (I only went down to 1 Hz, which is about the corner). All had an offset of about 33 uV. Note that all values are scaled to be referred to the input of the ADC.

It isn't clear to me why these look the way they do, but I haven't taken an analog spectrum of the inputs. I would assume there is noise at ~500kHz that is aliasing back, but I don't know what the source would be. Everything is under power with the bench supply, so there should be no switching noise. I also know that it does not come from activity on either of the SPI busses from previous work because disabling DAC updates or changing the block averaging of the ADC does not have any impact. I2C is routed nearby, but that was not active for these experiments. The UART is active, of course (that's where I got the data), but it is routed far away from anything. I suppose I'll have to get an analog spectrum at the ADC inputs to make sense of this.

@macaba - one final thing: what inspired that particular choice of values, and what driver were you using? Even if each driver is only seeing ~200 pF to ground, 4.7R seems like it might court instability.

[CurtisSeizert]

I took Mark's suggestion on the RC filter in front of the ADC, and it worked really well. I changed the values to 4R7/ 2.7nF CM + 10nF DM. The CM capacitance was chosen to limit the potential slew rate of signals at the terminals by keeping the RC time constant over 12.5 ns as mentioned in the datasheet. For the low gain setting, the NSD dropped from 3-4 to 1.51 nV/rtHz at 500kSPS and 2.5-3 to 1.50 nV/rtHz at 2 MSPS. It didn't really make sense to me that the NSD was as high as it was at 2 MSPS. Referred to the input at low gain, I was seeing about 0.3 nV/rtHz from the ADC + driver and reading about 1.7 nV/rtHz at the analog out but then seeing close to 3 nV/rtHz in the ADC readings. With the new RC filter here are the NSDs I got, referred to the ADC inputs:

fs = 500k; 55.40 nV/rtHz
fs = 1M; 43.66 nV/rtHz
fs = 2M; 35.94 nV/rtHz

If you plot the PSD against 2/fs for these values, by my math, the slope should be the square of the RMS noise of the ADC and the intercept should be the driver noise. The linearity with these three points is good (r^2 = 0.9998). If you extract the values from this, you get a driver NSD of 26.65 nV/rtHz and an ADC noise of 24.3 uVRMS. The driver noise is very close to expectations (LTSpice said 28 nV/rtHz), but the RMS noise of the ADC is about double what the datasheet lists as the typical value (12.5 uVRMS). The RMS value isn't just ADC noise though - it's also broadband differential noise at the inputs that can alias back into the passband as well as broadband common mode noise doing the same but reduced by the CMRR. The measured broadband NSD at the ADC inputs is actually matches the predicted value pretty closely without the 10nF DM cap, though that could be coincidental. I will probably try a simple 4R7/10nF (CM) for the version with the ADR1399 to see if that works any better. Either way, it seems that the values you would suspect should be fine (like 68R/2.7nF for 500kSPS and 33R/1nF for 2MSPS) leave quite a bit on the table. The predictions for system noise with ADI's online calculator do not match my results for those combinations with this topology, and the errors are numbers that are not convenient to express as percentages.

This is more of a general interest thing than of direct relevance to the NVM because 24 nV/rtHz at the ADC inputs is more than good enough to not impact the results with either gain setting. The mystery of the interaction between ADC noise and the input signal is still unsolved - note that here, the NSD at 500kSPS referred to the chopper input is 1.5 nV/rtHz though the ADC noise was greater than it was previously at 2 MSPS. My attempts to probe the input with a fast DC amplifier didn't find anything suspicious, but I was running into the noise floor of the instrument I used to get the spectra.

[CurtisSeizert]

I have gotten preliminary linearity results with both boards. The ADR1399 board looks good, the LTC6655 board not so much. I need to get my low-level source up and running to really figure out what the issue is with the ladder. I suspect it is related to intermodulation/aliasing as the points that were out of trend were also drifting a lot. I ran some long captures with both boards with the modulator frequency at 1800 Hz and averaging 30 cycles to get an output data rate of 60 Hz. A peak around 10 mHz was noticeable with the LTC6655 board, and I attributed this to the poor antialiasing performance of simple block averaging filters. I changed the code to allow higher order sinc filters (up to sinc3) because all the cascaded integrator-comb calculations can be done in fixed point. I ran a couple tests where I changed the ODR to 28.12 Hz (32 averages) to ensure there would be an alias of the mains frequency peak in the sinc1. The peak was not visible in either the sinc2 or sinc3 runs, but the sinc3 run had somewhat higher white noise density (about 10% higher), so I used the sinc2 filter for block averaging in another long capture with the LTC6655 board.

I got a bit more than 4 days of data before the BMS cut off the power, and the noise performance with the sinc2 filter was very good. The spectrum remained flat a bit below 1 mHz. There was a fair amount of drift (about 7 nV). I attribute this to the increased efficiency of the buck converters on the SMPS board at lower voltage. I did some regression analysis with time, input temperature, and the first derivative of input temperature as independent variables. I selected portions of the dataset where the correlation coefficient between temperature and time were low r^2<0.1 and got positive temperature coefficients of 0.25-0.6 nV/K. Obviously, this is not the best way of determining the tempco, but it is clearly quite small as there was quite a bit of temperature variability during the capture. The sensitivity to temperature change is between -1.5 and -2 nV*h/K. I think that both the drift and sensitivity to temperature change could be improved in a different case with the board supported differently. With the space taken up by 4x21700 batteries, there is very little extra room in the Hammond extruded Al case this was designed for.

The ADR1399 board does not seem to show the same downward drift as the battery discharges. I think this is probably because the increased efficiency effect is cancelled out by the increased current demand of the reference heater as the voltage between the heater pins drops. HTR- is supplied by the Cuk converter, so the associated components will dissipate more heat as the current increases. I included time domain plots and ffts for all these long captures. I RMS averaged the FFT data into logarithmically distributed bins to make it possible to see what is going on on the right-hand side of the plot.

I was underwhelmed with the performance of the Pomona low-thermal binding posts for this application because it really became critical to prevent air movement around them to reduce noise from transient thermal EMFs. I changed to a LEMO 0S size receptacle using the normal contact material, and that really helped. For some reason, it was also very helpful to put a CM choke at the input (just by wrapping the wires around an amorphous core to get about 1.5 mH). I don't have a shorting plug, but when I shorted the inputs at the end of a second receptacle and a length of cable, the offset relative to the internal short was about 200 nV, and that value seems to be reasonably stable.

I have identified a couple ways in which the protection on the power rails is inadequate, mostly by killing a couple AD4030s in fault states. In future revisions, I am going to add TLV431 + PNP clamps to most of the positive rails and increase bulk capacitance to prevent this sort of thing. The AD4030 (and probably the AD4630 as well) seems to be very susceptible to death. When the 1V8 rail had a transient overvoltage event from me accidentally shorting the +9V and +2V rails while I was probing the PSU (the latter supplies +1V8), only the ADC, two TMP117s, and the LDO died. All the glue logic and MCU survived unscathed. Also, the THP210 can actually pull the 5V4 rail above the absolute maximum for the AD4030 (I saw it hit about 6.5V) through the clamping diodes that limit the input signal swing. If the 1V8 rail dies, the ADC input switches do not turn off inputs above 5V, and that leads to another failure mode for the ADC. This is obviously problematic because any short to ground on the 1V8 rail will definitely lead to the death of the ADC.

[Echo88]

Maybe a variation of the overvoltage protection circuit figure 91, page 27 is also interesting in your rail protection case?
https://www.analog.com/media/en/technical-documentation/data-sheets/ada4177-1_4177-2_4177-4.pdf / https://opendcm.blogspot.com/2020/04/revised-analog-front-end-over-voltage.html
Cant remember if i already proposed it. I need to do some simulations on it myself, as it seemingly avoids the necessary transient reducing bulk capacitance.
Losing those high cost ADCs surely brings a tear to the eye. 

[CurtisSeizert]

When you lose one by shorting two pins while probing, it also brings some curses to the lips. I prefer to reflow BGA packages in the oven, so I had to take off a few of the though-hole compounds as well. No fun.

It seems like opencdm version of that protection circuit has an issue because it allows the input of the op amp to go two diode drops above the positive rail, but the idea in the ADA4177 datasheet is pretty cool. In this case, I think it will be easier to use clamps on the supplies as I mentioned because you only need one per rail (for the +5V4 rail) and you get protection against unforeseen causes of overvolting a rail, such as bridging two pins with a probe tip.