Low noise chopper and DIY nV meter

[dietert1]

Seems your case is similar to the Keithley 2182A nanovoltmeter. Its lowest range is 10 mV, which means 1 nV is 10 ** -7 of its range.
The lowest range of our Fluke 845A is 1 uV and the Keithley 148 does +/- 10 nV. Both support manual offset adjustment like a scope.

Regards, Dieter

[CurtisSeizert]

Before thinking more about another ADC one should look at the switching transients with a scope.

Good point. The experiments with this take a long time, so it is easy to get ahead of oneself. The capture currently running is 30 h in the temperature chamber to get a feel for the intrinsic drift as the battery discharges. At the moment, that looks to be a key source of drift, probably due to the decreased dissipation in the LDOs as the battery voltage sags. Hence my thinking about SAR ADCs.

[Kleinstein]

I think a faster ADC makes absolutely sense. This would allow to skip some time just after switching to reduce the effect of the settling phase at the cost of only slightly more noise / more averaging time needed. The other point would be doing the VOS corretion digital and having the option to turn the correction off to operate the amplifier in non chopped mode to look at faster signals.

A change in the thermals when the battery drains is perfectly plausible. The thermal can also effect the regulators and this way the voltage.
The circuit as is has a few points where the supply voltage can also have an effect:
The neg supply sets the current through R26 / R27 and R41 provides some current depending on the positive supply. The supply voltage effects the heat at Q9 and Q13.


@dietert:
yes the circuit is similar to the K2182, but with more gain and a little less noise. The Keithley meter also has a noise BW problem with the ADC: it can choose AZ mode for the ADC at the cost of extra noise BW or use the non AZ mode for the ADC and thus add a little drift from the ADC part. AFAIK the AZ mode does not work well with analog filtering, which is a petty.
The FLuke 845 is a different class of instrument: it is made for low leakage and high impedance sources. Alone from the resistors used for protection and filtering it is much higher voltage noise. A 1 µV range looks good, but this is with an analog meter and thus rather limited resolution and no longer stable in the lowest range.

[dietert1]

Let's try once more: The input range of the ADC depends on the reference voltage that can be some volts. The gain is 1000, so probably the nanovoltmeter input range is some mV and 1 nV will be below 1 ppm of the ADC. I think with some more gain and an input range 100 uV the ADC should be less of a limiting factor.

Regards, Dieter

[CurtisSeizert]

The input ranges are +/- 2 and 20 mV. At gain of 1000, the requirement for ADC noise is not particularly stringent. Just hitting 1 nVRMS requires one to have an ENBW of <1 Hz at the ADC, which means averaging will be required. Several commercially available precision ADCs implement some type of autozeroing to keep the NSD flat, and for those that don't, one could use CDS to keep it flat over the range where one is averaging readings.

As for the design, it is similar to the 2182a, but that doesn't implement the Vos correction block using the second diff pair (to my knowledge - I don't have full schematics). This was important to me because it enables one to have a high Ciss without necessitating pre-charge cycles to avoid large switching transients (or some other charge injection mitigation technique). The inputs are at very nearly the same voltage, so the main source of current noise should be charge injection from the TMUX1133. My goal was to have something approaching the performance of the nV preamp reported by a group at PTB(1), and I undertook the design by asking how could one implement something like Jim Williams's servo-offset-stabilized diff pair designs without needing to hook an AZ op amp up to the inputs. By the way, that group reported a design with improved current noise later (2016 I believe), but I don't have the reference handy. It was the same PI.

(1) D. Drung and J.-H. Storm, “Ultralow-noise chopper amplifier with low input charge injection,” IEEE Trans. Instrum. Meas., vol. 60, no. 7, pp. 2347–2352, Jul. 2011.

[CurtisSeizert]

First, I took a 32 hour capture of the instrument in a temperature chamber at 20 C. The reason for the "jump" (this actually happened over a minute or so) at 20ks is not clear, but the general downward trend is consistent with the trend I have noticed of residual offset being correlated with battery voltage. At some point, I will power it with a bench supply in the temperature chamber and see if that downward drift goes away. This supports the notion that periodic signals (time periods in the hour range) in the first captures I showed were due to environmental influences.

I got waveforms and spectra, and there is nothing in the frequency domain that seems to explain the discrepancy between the ADC noise density and the DMM noise density. I am going to guess that Kleinstein will say this is begging for conversions to be done in sync with half clock cycles, and if that's the case, then I agree. The transients settle quickly, but they are not symmetrical with respect to the DC bias voltage, so filtering them out could lead to nonlinearity. Most of the scope captures I took were several averages, so this is not clear from them, but the peak amplitudes of the switching transients are somewhat variable for each polarity. I averaged the settled values for each level from a scope capture (which itself took 10k averages) and they are 179 uV apart at 1000x gain. I have attached a handful of captures to show the waveforms at various nodes.

I probed around and ultimately took a spectrum of one of the ADC inputs, and I believe I figured out why the ADC was giving worse noise than the DMM, and the reason is extremely banal. I put input protection Schottky diodes on the bottom layer and ran the UART lines fairly close to them. The UART was running at 921600 Baud, and f_s for the ADC is 1.8 MHz, so the harmonics were probably aliasing. To fix this, I just ran the UART transaction before getting the data from the ADC (hence 1 cycle latency for output). The line is silent during conversions, and just like that, the noise density went down by more than 30%. My preliminary capture put it at 1.25 nV/rtHz, but I don't think the output was fully settled. This goes without saying, but I should not have routed a data line near an ADC input.

[dietert1]

Can you measure current into the diodes D2 and D3? They could have 100R resistors to Gnd, like R24 and R25. Certainly the MUXes will inject spikes there and asymmetry may cause DC. Such errors are attenuated by the outer feedback loop, but still you want them to be small.

Regards, Dieter

[Kleinstein]

The captured traces show quite fast settling, though with quite some ringing at 2 frequencies. The faster part (some 20 MHz) looks like it is strongest at the Q5 transistors. The collecors ar tightly coupled tot he rest, so it is a bit tricky to slow it down or dampen it seprately. Chances are less gain for Q5  (larger emiter-resistors R39,R43) could help with this. The frequency is that fast that also inductive coupling and LC resonaces may start to become an issue.

There are also quite some spikes at different times - maybe this is the UART or something else, as it looks much less frequent. At least that part should be avoidable.

The residual offset looks relatively small though still detectable (some 0.2 mV range for the output correcponding to 1 µV or 0.1 µV of offset for the FET amplifier depending on the gain used). This should be good enough and I don't think one would need to improve on this.

The capacitor C42 looks quite small, an I am not so sure that capacitance to ground would be right thing there. The input signal to Q8 is more relative to the +5.4 V supply so capacitance to the + supply may make more sense (could still keep C42 as it is small anyway).

[dietert1]

The same applies to C44 and C45. They could rather be 1 nF to increase the snubber time constant from 1 nsec to 100 nsec. And the input side of MUX U6A and U7A could have snubbers, too - maybe in addition to or instead of the diodes D2 and D3.

Regards, Dieter

[Gerhard_dk4xp]

A quick comment - it is rare to see well designed circuits like this built and tested, so thank you for sharing and please keep us up to date.
A bit of anecdata that may or may not be useful - TMUX1133 gives zero charge injection with near-0V input when run with asymmetric supplies (from my notes: +3.5V and -1.4V).

....
Regarding the TMUX1133 charge injection, is that point the same for both source and drain charge injection? If I can solve the problem simply by varying the supplies appropriately, that would be ideal.

I have tried a similar chopper some years ago using ADG819 / ADG841 as switches.
The charge injection could indeed be minimized by adjusting the supply voltages.
The problem is that the switching levels move also. The CPLD creates the clocks ,
also the delayed ones for the demodulator.

I decided to try EPC GaN Fets with their small absolute capacitances and build
a modulator in a corner of a different board that I had to do anyway. They are called
"power FETs", but are only  0.9 mm * 0.9 mm nekkid chips with 4 solder balls.
The manufacturers layout decal reqires to pull the solder mask ON the perimeter of
the pads. That prompted an email from JLCPCB. I waived that.
The GaN-FETs need > 3.5V gate voltage for low channel resistance; more than 6V
will kill them. The drain side is much more robust, so the drain should point to the
amplifier input.
 
The idea was to check if I could solder them at all. It was unexpectedly easy. Just use
a TINY amount of hot air or the FETs will fly away for good.

I did not test the modulator; it is constantly second winner against my other projects.
The circuit is only half the modulator, there should be 2 more transistors with opposite
clocks to create AC- for the post amplifier input.

[CurtisSeizert]

The captured traces show quite fast settling, though with quite some ringing at 2 frequencies. The faster part (some 20 MHz) looks like it is strongest at the Q5 transistors. The collecors ar tightly coupled tot he rest, so it is a bit tricky to slow it down or dampen it seprately. Chances are less gain for Q5  (larger emiter-resistors R39,R43) could help with this. The frequency is that fast that also inductive coupling and LC resonaces may start to become an issue.

There are also quite some spikes at different times - maybe this is the UART or something else, as it looks much less frequent. At least that part should be avoidable.

The residual offset looks relatively small though still detectable (some 0.2 mV range for the output correcponding to 1 µV or 0.1 µV of offset for the FET amplifier depending on the gain used). This should be good enough and I don't think one would need to improve on this.

The capacitor C42 looks quite small, an I am not so sure that capacitance to ground would be right thing there. The input signal to Q8 is more relative to the +5.4 V supply so capacitance to the + supply may make more sense (could still keep C42 as it is small anyway).

I can't guarantee the faster ringing is not a probing artifact. I was holding two probes against 1 mm diameter test pads at the same time for those, and spring clips for grounding was not an option. Note that the Q5B trace is 5 mV/div but that the same ringing is present on the clock signal, though it looks cleaner because the scale is larger. I will check that out when the current experiment is done.

I am not sure the source of the spikes, but the timing is not right for it to be anything with the MCU because it happens in both phases of the clock cycle. The UART and SPI transactions both happen at the beginning of MOD_CLK being low.

The amplitude of the square wave taken at the SMB jack (J18) is 178 uV (allowing for 500 us settling). From observing the warm-up transients a number of times, I think the residual Vos before parasitic thermocouples come into play is very close to this, but this could also be a product of the settling behavior of the Butterworth filter.

C42 at 10 pF was helpful in simulations for improving settling time, and it was much more effective than increasing the size of C48 to increase the integrator time constant for the Op amp CM servo. It has to be small to keep that loop stable. Tying it to Vcc would have been better, but it should be fine for now.

The same applies to C44 and C45. They could rather be 1 nF to increase the snubber time constant from 1 nsec to 100 nsec. And the input side of MUX U6A and U7A could have snubbers, too - maybe in addition to or instead of the diodes D2 and D3.

Regards, Dieter

C45 doesn't act like a snubber, and after I built this up I re-ran simulations without R25 and found it to be unnecessary. This is in contrast to my LNA, which does require resistance in parallel with the integrator capacitor for stability. Anyways, these definitely need to be small to keep the loop stable, at least with the current values of Cf (33 pF now - modified since uploading the schematics). The integrator capacitor is meant to cancel the the effect of the input capacitance of the op amp. The snubber on the non-inverting input of U5 is to keep the impedances on the output of the diff pair balanced.

Can you measure current into the diodes D2 and D3? They could have 100R resistors to Gnd, like R24 and R25. Certainly the MUXes will inject spikes there and asymmetry may cause DC. Such errors are attenuated by the outer feedback loop, but still you want them to be small.

Regards, Dieter

I have no way of measuring this current directly, but one could infer it from the voltage at those nodes. Putting resistors in series with these could be an option, but I think this would maintly serve to damp any effects of the junction capacitance of the diodes. In simulation, these nodes all stay within 5 mV of ground, but this is with ideal switches to keep simulation times reasonable.

Overall, I have spent a lot of time simulating various iterations of this, and I don't think I left much on the table for improving transient behavior around switching times. That said, I don't really know what I'm doing, so it could be a deficit of imagination on my part. I am not going to say that every value here is optimal, but they were all chosen on purpose. That said, there may be some room to reduce the gain of the offset correction diff pair. I think one could get more mileage from a deglitching filter, converting in sync with each phase of the clock cycle, or both. Both would be ideal for reducing the tension between frequency rejection and settling time requirements for an antialiasing filter.

Finally, I have some preliminary Vos tempco data, but this is still provisional until I can synchronize my TECsource with reading the serial stream of data that the instrument puts out. If the TMP117 were operational, that would also help. Anyways, it's less than +2 nV/K (from ramp slope), though probably closer to +1 nV/K (from settled values at each end of a 10 C ramp). With a +0.1K/min ramp, the displacement during the ramp is on the order of 30 nV, so under all normal use cases, dT/dt would be more important. I think that's a good sign, because it can be addressed more easily with appropriate thermal isolation slots, etc.

[CurtisSeizert]

I have tried a similar chopper some years ago using ADG819 / ADG841 as switches.
The charge injection could indeed be minimized by adjusting the supply voltages.
The problem is that the switching levels move also. The CPLD creates the clocks ,
also the delayed ones for the demodulator.

I decided to try EPC GaN Fets with their small absolute capacitances and build
a modulator in a corner of a different board that I had to do anyway. They are called
"power FETs", but are only  0.9 mm * 0.9 mm nekkid chips with 4 solder balls.
The manufacturers layout decal reqires to pull the solder mask ON the perimeter of
the pads. That prompted an email from JLCPCB. I waived that.
The GaN-FETs need > 3.5V gate voltage for low channel resistance; more than 6V
will kill them. The drain side is much more robust, so the drain should point to the
amplifier input.
 
The idea was to check if I could solder them at all. It was unexpectedly easy. Just use
a TINY amount of hot air or the FETs will fly away for good.

I did not test the modulator; it is constantly second winner against my other projects.
The circuit is only half the modulator, there should be 2 more transistors with opposite
clocks to create AC- for the post amplifier input.

Thanks for the information about the charge injection. I had also considered using the EPC GaN FETs, but the gate leakage in the datasheet was very high, and I didn't want to make a custom board just to test that. I have used their UPC1966 gate driver in 0.4 mm pitch BGA. I had to use a microscope to place it, but with the reflow toaster oven soldering it is no big deal. Still, for fine pitch BGAs, I find myself in a position of really needing a good reason to use them to spec them on a board that I am inevitably going to hand assemble.

[CurtisSeizert]

I did some investigations around current noise in hopes of minimizing it in the next revision. In one experiment, I partially populated a board with a TMUX1133 and some decoupling caps. I powered the chip with a DC supply at 5.5V and connected VSS to the output of my signal generator to see how viable varying the VSS would be for minimizing charge injection from the input switch. I measured charge injection at the drain by tying it to GND with 1k. The two sources were tied together and held at ground potential with 1k as well. Charge injection was minimal here. I don't know if that's because it was faster than the LNA could measure, but most of the disturbance around switching transitions was just due to ground loops in my setup. I tested this by biasing the switch signal high enough that the switch would always be on and got about the same result.

For the whole nV meter, I measured current noise across a 100R resistor with the LNA with and without the input capacitor. I attached two spectra from this and a time domain plot of the switch transition. It is worth noting that both the rising and falling edge of the clock give the same polarity spike. Note that the horizontal scale is 10us/div. I have been messing around with simulation models to see what I can do to improve this. My working hypothesis at the moment is that most of this is coming from the transition spikes applied to the inverting input of the diff pair via the Cgs of the JFETs.

In various simulations I have run, it seems like the demodulator switch is a large source as well with the injected charge mostly travelling from output to input of the differential pair. Buffering the outputs with emitter followers helped a lot for that, as did adding in my estimates of the parasitic capacitances of the nodes in the diff amp. I think it will be important to get the switching transitions as clean as possible to get optimal current noise.

[NWerner]

I am not sure, whether I understand your description correctly but I will add my 2ct nonetheless:

As far as i know, charge injection (unless somehow compensated) is directly influenced
by channel-characteristics -  so that parts with lower rdson exhibit higher charge injection. TMUX1133 is
rather low-ohmic.

charge injection results from accumulation and redistribution of charge at gate and thus heavily
depend on impedance at source, drain and substrate(?). Lots of IC-lvel circuit tricks are used to
not reduce charge injection  but to make it constant. Maybe a JFET shows fundamentally different behaviour.

[CurtisSeizert]

As a quick update, I am in the midst of redesigning the schematic for a second revision, and I have decided on the broad strokes of how everything will be done. The chopping switches will both be PE4140 quad SOI MOSFET arrays. These are designed as RF mixers and have very low parasitic capacitances. This was an idea I got from (Drung 2015), which is a good reference for current noise in choppers. They measured 3 pF from drain to drain. I measured 1.2 pF from gate to drain, but I am not really set up to make measurements of such small capacitances accurately. I haven't been able to find anything about the structure of this particular FET array, but my assumption is that the distinction between drain and source is arbitrary since the bulk is floating. At 9.5 mA drain current, I measured Rds(on) of 6.5 Ohms for my sample, so the Ciss*Rds FOM is much better than any FET or integrated switch I am aware of.

An interesting thing from Drung 2015 is that there will be excess current noise in a chopped amplifier even if there were no charge injection whatsoever. This is because the Johnson noise associated with the switch's resistance puts some variable charge on the chopper's load capacitance, and when the switch changes states, it samples this variable charge. The expression they derive for wideband excess current noise is i_n=sqrt(8*kB*T*C*fc). There is a 1/f term, but it's just to fit experimental data. The spectrum is flat (at 300K) to about 150 mHz.

When I built up a test jig for the PE4140, the SOT23-6 breakout board I mounted it on had a fair amount of capacitance between one gate and drain, so there was a good deal of feedthrough. I found that by varying the high voltage for the gates to compensate for the difference in capacitive coupling, it is possible to nearly eliminate the current spikes at the input terminal. This is the strategy I am going to use for minimizing charge injection, along with careful layout to minimize coupling. Of course, all the gate signals will be bootstrapped as well. For the demodulator, I will also use a PE4140 but reduce the gate swing to about 1.8V.

V_os compensation will happen through a digital control loop so that I can turn it off and not have things go haywire, this necessitates using a SAR ADC for higher speed and low power consumption, which will be the AD4032-24. The scheme I have for driving the ADC at the moment gives me about 2 mA of quiescent current, so the overall power consumption will still be much better than the LTC2442. I'll post the schematic for the revision when I finish it.

Drung, D., Krause, C., "Excess Current Noise in Amplifiers with Switched Input" IEEE Trans. Instrum. Meas., 64, 6, 1455-1459, 2015.

[ArgyllGargoyle]

As you probably know, you can cast this noise expression as the thermal noise of the equivalent resistance of the switched capacitor.

Did you happen to evaluate the gan fets from epc?

[Gerhard_dk4xp]

I'd find that interesting, too.  :-)

BTW I stumbled across that paper from univ Twente:
<     https://ris.utwente.nl/ws/portalfiles/portal/5337827/Klumperink05reduction.pdf       >

It seems that the traps that generate 1/f take some time to come into existence after
switching a transistor ON. That could be a low-hanging fruit in a chopper amplifier.

Gerhard

[ArgyllGargoyle]

Gerhard,
I was hoping you would chime in - can you tell us any more about the epc devices in this context?

[CurtisSeizert]

I didn't try any GaN FETs because the datasheet numbers I saw for gate leakage were too high. I don't know if they were limited by what they could measure, but even their smallest one is listed as having a typical leakage current of 100 nA at Vgs=5V. I believe their devices have a diode between gate and source to prevent Vgs from going significantly below 0 V, so that could be the source of the leakage. The Ciss of the EPC2038 is 7 pF (typical), which is certainly good for a MOSFET, but not as good as the PE4140. On the whole I don't think it compares favorably to the PE4140 for this application. If I am feeling masochistic, maybe I'll make a 0.4 mm pitch BGA breakout board and put it in my next JLC order, but I am not getting my hopes up for reasonable gate leakage.

It seems like the group from PTB tested some other FETs for their current noise investigation but that the results are in the master's thesis of one of the coauthors (Christian Krause), which I was unable to find. I looked around, and there really are not any other FETs I am aware of that are close to the PE4140 (besides the PE4141) for this. Presumably this is because SOI FETs tend to come in the form of ICs, and the other small Si FETs have ESD protection that compromises leakage. The PE4140 is only rated for 100V HBM, so the ESD protection is minimal, which is kind of scary with such a small Ciss. By the way, all JFETs that have a sufficiently low Rds(on) to not compromise the voltage noise of this amplifier have much larger parasitic capacitances.

[Kleinstein]

For the current noise it should not be only about the capacitance of the switch FETs. The input capacitance of the amplifier (e.g. JFE2140) should also matter. As far as understand it this is related to the so called reset noise with a capacitor. When disconnecting a capacitor there is a sqrt(kb*T*C) noise in the charge of the capacitor and thus the corresponding current just before disconnecting and when connecting again to the other side.

So there is a downside in parallel connection of multiple units instead of a bit higher current per JFET.  As the swtching is usually very fast the cascode part may not be effective in reducing the capacitance.

Compared to ready made chopper OP-amps it helps that the chopping frequency can be relatively low. In certain range one could adjust it depending on the needs and balance between current noise and 1/f noise of the JFET stages.

I would not worry that much about the current noise. The current noise would be relevant only with a relatively high source impedance and that would create quite some thermal noise, so that one would not be able to measure in the nV range anyway and would want a different amplifer. Even with a little higher capacitance from standard CMOS switches the current noise is not that large.
The PE4140 still looks interesting.

[CurtisSeizert]

I am not too worried about current noise, but I would like to keep it as low as possible to be able to measure bridges without the noise figure getting excessively high at source impedances of 10k. With the modifications I made to the diff amp, the differential input capacitance in simulation is 37 pF for most of the bandwidth (through 1 GHz). I think the bandwidth of the cascode only needs to be higher than the f_t of the input JFETs to ensure the Miller effect is suppressed for the whole BW, and this appears to be the case at 800 uA/JFET with the HN4C51. That means an effective capacitance of 74 pF for the sake of current noise calculation, which is acceptable. There is an interesting tradeoff here because larger JFETs usually have lower 1/f corners, so you can chop at lower frequency, but the input capacitances are also higher.

It is worth mentioning that the experiment that turned me off of the TMUX1133 was that while I found it was possible to bias the supply voltages for zero charge injection to the source terminals on changing the state of the switch, it was not possible to do the same for the drain (common). That value was not very sensitive to supply voltage bias, and it was consistent with the ca. 3 nA bias current I observed with the whole amplifier at f=330 Hz. This is not to say there aren't other potential analog switches for the input chopper, but I felt compensation would probably be easier with discretes where I have access to the actual gate drive signals. That said, this is clearly not an application that manufacturers have targeted for discrete MOSFETs because most are not suitable, usually because of gate leakage through ESD protection structures (this is generalizing the ones I have looked at, so there may be some good ones I missed).

The other potential solution I considered, which you could use with discretes or ICs, is to essentially do what the 3458 does and use two multiplying DACs to inject charge at the JFET gate nodes in opposition to the charge injected at the input terminal. This is somewhat complicated to implement though, and the correction charge injection is never perfectly coherent with the charge injection being cancelled out. I believe you could go further and attempt to cancel the incoherence of these with a capacitor between the input node and some further correction signal, but that seems like it would be very tricky to get right. It is definitely advantageous to start with a FET requiring the smallest possible gate charge to bring the device into full conduction. With the PE4140 that seems to be small enough to depend more on PCB layout than on the device itself.

[Kleinstein]

For the switching spike and maybe also the input bias current different switches / fets do make sense. The ready made switch chips tend to switch fast (e.g. 200 ns and faster), while the discrete fet switching often gets relatively slow. In the HP3458 this is needed, so that the DAC part for the compensation can follow. A 3 nA bias for the amplifier is indeed not good.
I once did a quick test for a similar type chopper with 74LV4053 switches and there the charge injection was reasonably low. The on resistance may however be a bit on the high side (20 ohm range).

[CurtisSeizert]

I had a test board made to get a better idea of how feasible it would be to minimize average Ib and spikes by individually controlling switching levels with a PE4140-based chopper. On the board there is a transimpedance amplifier to measure current flowing into the input node. I built a couple up with different transimpedance configurations (One used an LTC6240HV with 100M | 6.8pF, the other used an ADA4637-1 with 10M | 2.2 pF, both had 22 pF to ground at the summing node). With both of them I used a trim pot to get the output within 2 uV of ground when it was disconnected from the FET. With the more sensitive amp, I found the gate leakage current to be negligible at all gate voltages (well under 100 fA). By individually adjusting the low voltages for each gate, it was possible to get the average input bias current <10 pA at 1 kHz. I had it in the neighborhood of 1 pA for a while, but it drifted back up to a few pA. This required mV resolution on the gate voltage adjustment. On the board with the faster amp, I got a minimum bias current of about 16 pA.

With both of these, minimizing the bias current required increasing the low voltage so the FET array was not totally off. I haven't determined r_off under these conditions yet, but it's probably in the neighborhood of 1M. I don't see this as a huge issue in the application as the residual offset of the nanovolt amplifier is <1 uV, so that would be <1 pA flowing from the feedback terminal to the input or vice versa. For this test, however, it did mean there was some current flowing in either static position of the switch, probably due to the FET acting as Rg of an inverting op amp with some offset on the summing node being amplified. Subtracting the average of the currents when the switch was in either static position, I was able to get the current due to chopping down to about 5 pA for the ADA4637-1 board. I was sick of messing with switching voltages at this point, but I saw that on both sides of zero, so I think this should be a viable solution.

I have attached a couple scope traces with the ADA4637-1 board to show the switching spikes. The duty cycle of each clock signal is 49.999% in the first and 50% in the second.

Edit: The second trace didn't seem to attach the first time. Added it.

[CurtisSeizert]

I have just finished the schematics for the second revision of the nV meter (attached). There are some things with the MCU that aren't finalized yet since I will probably be writing some of the code while I work on layout, but other than that things are close to finished. There also may be some resistor and capacitor values for non-critical things that I change as I go on.

The general idea is along the lines of the modifications that Kleinstein and others suggested with switch gate drives as I mentioned previously. The modulator and demodulator both use PE4140 quad MOSFETs instead of integrated switches. Unlike the proof of concept version, the Vos correction feedback loop is digital, so chopping can be turned off to measure fast signals. The offset will be calculated from by doing analog to digital conversions in each phase of the clock cycle and the DAC output adjusted to minimize the change in voltage between the two phases. Similarly, there is a relay to set the source impedance to 10k and that can be used to adjust the gate drive voltages to null the input bias current. Each gate drive clock signal is independent, so dead time can be configured separately for both the modulator and demodulator. I have also added an isolated external trigger that can be used to synchronize conversions or chopping cycles to some external clock source.

The ADC driver is certainly more complex in this case than the LTC2442, but the quiescent current draw should be reasonably low (about 3-4 mA depending on whether ADA4807-2 or ADA4805-2 is used as the driving op amp). It is a composite fully differential amp using a THP210 and a pair of fast op amps, which allows a straightforward implementation of CDS in order to null the offset of the ADC/Driver independently of the chopper input stage. Hopefully using an LT5400 will keep gain consistent within a few ppm over the input voltage range. The individual resistor values would need to be 1k or 10k in that case. The chopper stage is largely the same as before with a few modifications to lower input capacitance, minimize feedthrough from the demodulator, and reduce quiescent current draw.

It was important given the lessons from the first revision to reduce power dissipation, so there will be an external module that uses buck converters (probably using LT8608s) and a Cuk converter (haven't decided on the controller) to generate the input voltages for the LDOs on the board from 4S Li cells. The whole digital section runs at 1.8V (save for the isolators, which will run at their minimum of 2.5V) in order to further reduce power consumption. I noted in the proof of concept model that the board was not particularly EMI sensitive as there was no immediate change in offset voltage when I charged the batteries while continuing conversions, so I think a switchers with tight layout and some shielding should be OK.

[Kleinstein]

The circuit looks quite complicated.

The part around U9A is still a bit sensitive to supply noise, as it mixes parts relative to the pos and neg supply and Vcm.
As a more minor point, R82,R83 look rather high: with so little current the emitter follower may not help much.

I don't hing the CD4051 mux chips are strong enough to drive the relays. This is at least a rather unusual way to drive latiching relays.

I don't think one would really need JFETs (Q16-Q19) as low leakage diodes - the BAV199 should be good enough here. This is especially with D15 as an additional leakage path. Usually one should get away without D15, the OP internal diodes and R94 should be enough to protect the OP-amp. It is also a bit unclear what the target is for the input bias / leakage. There is also the comparator part at the very input that could add leakage that is higher than the diode protection.

Similar the target level of protection is a bit unclear.