Low noise chopper and DIY nV meter

[CurtisSeizert]

Well, I missed the boat on the nV design challenge, but I have been working on a nV meter which is at the proof-of-concept stage and thought I would share the design for the benefit of those who are interested. At this stage in testing and writing code, it is more of a DC-accurate LNA, and I will include that block of the schematic as I clean up the rest of it. In the name of getting a handle on how this behaves, I didn't get into charge injection cancellation for the input switching, but as I will explain below, a main motivation of the design is to enable minimal current noise while maintaining low voltage noise and drift. The noise spectral density I measured is 1.2 nV/rtHz, which is flat above 25 mHz, but I suspect some of the apparent 1/f noise is the product of thermal variability. Calculating this out, the 0.1-10 Hz p-p noise is around 22 nV (99.7% probability). I haven't measured thermal drift per se, but the natural experiment of living in an old house with no insulation as winter approaches allows me to put it at <7 nV/K. Again, I suspect that further testing with a fully assembled instrument will bring this number down. With a switching frequency of 330 Hz, the residual offset is about 550 nV, rising to around 670 nV at 990 Hz and 1.2 uV at ca. 5 kHz. The time domain trace I've attached is centered at ~550 nV, but I subtracted this offset for ease of interpretation. The heat kicked on around 12000s, hence the jump. It is probably mostly thermocouple effects at the meter terminals, which I'll have to shield in the future. The amplifier was shielded more from this, so I wouldn't expect it to react that quickly. In preliminary testing, the gain (1001x or 101x) does not impact the input offset voltage.

I adapted the design from an AC coupled LNA I have been working on and kept the skeleton of the input stage because I know it works. The modulator switches connect the input and feedback alternately between the two inputs of a differential pair, and the demodulator switches connect the outputs of this differential pair to the inverting and non-inverting terminals of an op amp. In itself, this would give a DC-offset square wave with an amplitude equal to gain * Vos of the differential pair and a pulsating input current proportional to Vos * Cin. The average value of this would be Vin * gain. To reduce the AC portion of this, the output is HP filtered and (re)modulated between a pair of integrators that drive a second differential pair that servos the current in each leg of the first one to drive the inputs to the same voltage. This considerably reduces clock feedthrough and input current pulsation.

There are a couple design choices I made whose motivation may not be immediately apparent, so I'll go into a bit more depth on those. The whole system is frequency modulated (I'll call this chopped despite some ambiguity in how this term is used) to avoid a noise penalty of 3 dB in sampled (time modulated or autozeroed) systems. Obviously, we do pay this penalty by using a diff pair rather than a single-ended amplifier, but I have seen a few time-modulated, single-ended designs, and exploring this topology was more interesting to me, so this is where I took the 3 dB hit. The main diff pair uses a pair of PNP BJTs in the "transconductance enhancer" configuration. Because the op amp output is single ended, the op amp has to go outside of the mod/demod block to keep the entire system frequency modulated. As such, the mod/demod block really just serves to attenuate the input offset voltage of the op amp by the differential gain of the long tailed pair. Ditto noise and TCVos, though the former is limited by the noise of the diff pair itself, and the latter is limited by parasitic thermocouples, etc. There is a limit to how far you can push this gain and have the circuit remain stable, which is why the Av=101 at DC divider maintains ~60 dB gain at high frequencies. One can imagine various ways around this, but for me that would have been more design overhead and (probably) complexity. Anyways, the transconductance enhancer helps push that gain as high as is feasible.

It is possible to construct this with a single integrator and an SPST switch, with the base of Q5B tied to GND. This works well with ideal switches in simulation, but it suffers more from the parasitics of actual CMOS switches. To the extent that the sources of U13 are matched with respect to charge injection, with dual integrators, that becomes a common mode term and is attenuated reasonably well by the CMRR of the servo diff pair. The HP filter and the integrators are both two pole filters, to improve rejection of signal frequencies near the switching frequency. Signals or "signals" that are coherent with the clock frequency (e.g., EMI from the clock traces) do lead to a Vos of the input diff pair, but this is modulated up to the clock frequency rather than appearing as a DC term.

Elsewhere in the design (I'll include the full schematics and design files once things are cleaned up), the clock signals originate from an STM32L432 running at 10 MHz (about 1.2 mA current draw). The output of this chopper-stabilized amplifier is fed through a fourth order Butterworth filter with fc=100 Hz using OPA2205A in a Sallen-Key topology. The data captures and FFTs I took were from the output of this filter. This is converted to a differential signal by another OPA2205A for conversion with an LTC2442. The digital output will be transmitted to a PC via UART (through an optoisolator) to USB with an FT230X. The whole thing draws around 32 mA on the positive rail and 27 mA on the negative rail. Also, there is a TMP117 on the board for monitoring temperature. All these elements are populated, but I haven't written the code yet.

Edit: corrected some erroneous values for resistors R41 and R56. Thanks to Kleinstein for catching this.

[Kleinstein]

Quite impressive performance and quite compicated circuit.

I see a slight problem with the offset correction stage around the NPN differential pair / U12. I don't see how the common mode voltage of U12A/U12B is stabilized / defiened. The control loop only uses the differential output. Though small, the input offset of U12A/B can make the common DC level drift away.  As a quick fix one could try a large resistor (e.g. 10 M) in parallel to C56 or C58. This would limit the gain of one side and this way fix the DC level, so that they won't drift away.

There is a slight chance that the time domain signal has  U12A/B drifting and at the jump get one of them to saturation so that one than gets more noise and a stable output.

I would not call the amplifier frequency modulation, but more like alternating offset. It is a little similar in this respect to the amplifier of the Datron 1281 and Keithley 2182, but with the extra offset correction loop. The correction loop is close to US 7,764,118.

Somehow the values for R30/R31 and R56 at the current source look like they belong to different design steps and amplifier working current. R56 suggests a rather low current of some 0.6 mA for the differential stage and R30/R31 want some 5 mA for the JFETs alone. So looks like one set is of by about a factor of 10. With the current values in the PDF plan Q10 and Q12 would be inactive.

[CurtisSeizert]

Thanks! I will admit, when I turned this on and saw the scope trace converge on zero, I was very surprised. You were right, R56 should be 150R, which I caught during assembly but forgot to update. Also R41 is 22k rather than the 28k7 I had originally, but that's not very important. I changed the schematic in my original post to reflect this. With the 13.65 mA tail current, somewhat less than half goes through the PNPs. The values were optimized for noise, and R32 and R44 were required for stability.

As far as nothing to set the common mode on the Q5 diff pair, I was worried about the same thing, and I don't fully understand why it behaves well, but it does actually seem to stay put, at least on the time scale of hours. If you set the INT_EN signal low, things go haywire very quickly, but when I have probed the bases of NPN pair Q5, they are actually fairly close to GND. You could say this is due to the parallel resistance of the integrator capacitors, which is about 10G, but it behaves well in simulation too. In simulations, I put resistors in parallel with these capacitors before I finalized the design out of fear this would happen, but taming the gain of these integrators that way limits the effectiveness of the offset correction loop. I also don't think the common mode for that pair is set by the finite impedance of the current sink because when I was building up the design in simulation, those current sinks were modeled with ideal current sources. I did simulate a number of scenarios using op amps with much worse Ib and Vos, but with the same op amp (i.e. delta_Vos=0 in simulation), the common mode stays very close to zero. I left one simulation running overnight and was satisfied that things would probably be OK, and if they weren't, I could just delete R47 and tie the base of Q5B to GND. I will have to record some numbers after I have left it on for a while to see if it drives either diff pair transistors or the current sink into saturation to set the CM.

I am pretty confident the jump was the product of the heat coming on, because it happened at 6:30AM, which is exactly when the heat is programmed to turn on. Also the meter is right under the vent, which is not the best, but moving it would mean dealing with the rat's nest of cables back there, so I have resisted. Anyways, just from how fuzzy the trace was after that jump, it looks like some of the LF noise was from air movement around the meter terminals.

[Kleinstein]

The expected drift for the common mode of U12 A/B is very slow. A few µV offset from the OP amps with 1/2 s time constant would be some 10 mV/h range drift rate.  So if it starts well, it may be OK for a long time.

Thermal effects can definitely cause noise. Parts that can be sensitve include the gain setting resistors via thermal EMF at the resistors (R2 and R76). Another issue can be filter capacitors like C56, C58. The supply can also have an effect at some areas, with thermal effects on the supply coupling to the output. Also light can be an issue for some parts.

[dietert1]

How do you know how well the multiple JFE2140 share current? Are they selected?
I mean the intended noise reduction depends on that. I remember inserting small source resistors into the Keithley 2182A input stage that has two discrete FET pairs.

Regards, Dieter

[CurtisSeizert]

Kleinstein - that's a good point. I've got another one that is half done, so I will populate the top of the board without the BMF gain setting resistors that I used and have that be my test case for various modifications. I know I can nail it down with another servo loop, but I feel that may be overdoing it on complexity. Laying out this block while being cognizant of thermal effects and minimizing parasitic capacitances that might lead to instability was a significant task already. I do very much appreciate the time and thought you put into looking at the design; I was excited to test a board and rushed some elements, and I didn't go beyond guess-and-check in simulation to consider how this would work over longer time periods. I also made some dumb mistakes, like tying the active low enable pin of the TMUX1133 modulation switch high, connecting UART TX on the controller to TX on the FT230, etc., that I would have caught had I reviewed the schematic more carefully.

Some additional things I have noted are that the residual offset is much lower without the covers on the shield frames - down in the range of 330 nV with both covers off. Putting each of these back on makes the offset voltage go up quickly - most of the effect happens within a second or two. When both are on (and the UART is idle), the Vos is around 560 nV, and the contribution from each cover is approximately equal. I do most measurements with them on because they serve well as thermal baffles to reduce air movement around the leads of sensitive components, but the noise is surprisingly good with them off, around 10-12 nV spread with the meter at 100 NPLC. The other thing that impacts the Vos, which I did not expect to be as significant as it is, is what code the uC is running. It seems like the most significant thing is how active the UART TX is because the optocoupler LED takes a fair amount of current with all that returning via GND. The GND connection for high and low inputs are parallel to this return path, with high being closer to the device, but they are about 50 mm away. I will have to look into this more, but it would obviously cause problems if activity on that bus were sporadic.

Finally, I did another long capture, this time with the meter terminals shielded. It was colder last night, and I think the periodic signal was cycling of the heater. Note that with the terminals of the meter shielded from airflow, this cycling did not cause the additional "fuzziness" as it appeared to in my previous capture with the meter terminals exposed. The struggle is real in this house with insulation. I can use my thermal camera as a stud finder even if the outside temperature is just a few degrees different. I will need to simultaneously record temperature going forward to make sure this is what's going on.

[CurtisSeizert]

How do you know how well the multiple JFE2140 share current? Are they selected?
I mean the intended noise reduction depends on that. I remember inserting small source resistors into the Keithley 2182A input stage that has two discrete FET pairs.

Regards, Dieter

I did not select the JFETs, but I have previously tested 40 or so of them from two different orders. The matching from ones within the same order is good - with my samples, the spread was around 25 mV within a lot, so the current sharing should be close enough. They are running at around 800 uA drain current per FET, which should be around 7 mS transconductance, so a 25 mV difference between high and low would only equate to around 175 uA spread of drain current. So you would have one FET drawing 11% more than the average and one drawing 11% less, which won't have a big impact on noise, which will vary inversely with the fourth root of drain current in the square-law region. This is not a gamble I would make with any other JFET pair, but I am comfortable doing it with the JFE2140.

[dietert1]

I have been using the 2182A with a DIY low thermal EMF relay scanner and used one input with an internal short to zero the meter once a minute or so in the analysis software, with good results. Similar thermal EMF may occur on other scanner inputs. Getting the last nV isn't easy. Some people use a temperature chamber to put the whole setup inside.

Regards, Dieter

[Kleinstein]

If one really wants one could improve the current sharing with source side resistors for JFET pairs. So 1 resistor per pair, not per transistor. This would not add extra noise, like classical source resistors.

The ground should normally be separate for the critical signal part and the supply. Besides the ground side it may also be via the supply. The way the amplifier is build, it may be somewhat senstive to supply variations (e.g. with the resistor from the +5 V to the cascode base, or at the loop for the folded cascode.

If really needed one could use a constant current for the OK and then shorten out the LED of the OK with FET to turn it off.

One could probably use considerably larger resistors for R39 / R43 / R55 and this way make the offset correction loop lower gain at the BJT pair and to compensate use smaller resistors for the R48/R50. Chances are one could also get away with a non AZ OP for U12. Chopper stabilized OPs are potential noise sources via EMI I would avoid if reasonable possible. Also an AZ OP-amp with 1 M range resistors at the input is not ideal. I don't see a real need for the relatively expensive SSM2122 transistor pair if the effect on the offset is small.

It looks there is indeed quite some thermal effect. There are many possible source for an offset in the 500 nV range and they can in part compensate. So keeping the lids on is probably good.

[macaba]

A quick comment - it is rare to see well designed circuits like this built and tested, so thank you for sharing and please keep us up to date.
A bit of anecdata that may or may not be useful - TMUX1133 gives zero charge injection with near-0V input when run with asymmetric supplies (from my notes: +3.5V and -1.4V).

[CurtisSeizert]

If one really wants one could improve the current sharing with source side resistors for JFET pairs. So 1 resistor per pair, not per transistor. This would not add extra noise, like classical source resistors.

The ground should normally be separate for the critical signal part and the supply. Besides the ground side it may also be via the supply. The way the amplifier is build, it may be somewhat senstive to supply variations (e.g. with the resistor from the +5 V to the cascode base, or at the loop for the folded cascode.

If really needed one could use a constant current for the OK and then shorten out the LED of the OK with FET to turn it off.

One could probably use considerably larger resistors for R39 / R43 / R55 and this way make the offset correction loop lower gain at the BJT pair and to compensate use smaller resistors for the R48/R50. Chances are one could also get away with a non AZ OP for U12. Chopper stabilized OPs are potential noise sources via EMI I would avoid if reasonable possible. Also an AZ OP-amp with 1 M range resistors at the input is not ideal. I don't see a real need for the relatively expensive SSM2122 transistor pair if the effect on the offset is small.

It looks there is indeed quite some thermal effect. There are many possible source for an offset in the 500 nV range and they can in part compensate. So keeping the lids on is probably good.

I agree with a lot of those points, especially the lack of need for the SSM2212. I think one of the standard SOT363 rotatable transistor pairs, perhaps the MBT6429, would be appropriate. The influence of that part is negligible, so the exact choice shouldn't matter too much. Regarding the signal GND, I did connect IN- to GND at the FB resistors, but the relay short is connected to GND at the lead of the relay, which puts the two points about 27 mm apart. I probably should have routed IN- through the relay to cancel some of the thermal offset from that, so I will incorporate that in a future revision. At present, it seems that current on GND is the largest individual source of error.

I was somewhat ambivalent about the choice of integrator op amp, and I believe I specified the OPA2186 prior to increasing the integrator resistors to 1M. The OPA2192 would be a better choice at this stage, but the only ones I have of those on hand are MSOP, and the footprint is SOIC.

I have been using the 2182A with a DIY low thermal EMF relay scanner and used one input with an internal short to zero the meter once a minute or so in the analysis software, with good results. Similar thermal EMF may occur on other scanner inputs. Getting the last nV isn't easy. Some people use a temperature chamber to put the whole setup inside.

Regards, Dieter

I'd like to get the ADC working before I put it in a thermal chamber so I can transmit readings and board temperature via USB, but I will ultimately do that testing. A goal with the TMP117 is to be able to do first order temperature compensation so that it's possible to get close without needing extreme temperature stability.

I will keep a list of these things on hand for next revision, but I would really like to implement some sort of charge injection cancellation in that. One of the things I am wondering there is whether a really effective solution exists for integrated switches because the level-shifting is internal. With the TMUX1133 the point where the curve in the datasheet passes through zero is more dependent on signal ground than VSS, but this is only for charge injected at the drain for a given source voltage. With the TMUX6119, they give figures for both directions, and they seem to cross zero around the same point, so using a DAC to set logic ground for the switch with appropriate level shifting may be feasible. I think any way you slice it, a DAC will be necessary, so that is probably the simplest solution. I do get the sense that cancellation down to the ~10 fC  or lower level this way would be quite difficult. Anyways, if anyone has other ideas or lead references, I would appreciate those. Most of the material I have found deals with IC design.

[CurtisSeizert]

A quick comment - it is rare to see well designed circuits like this built and tested, so thank you for sharing and please keep us up to date.
A bit of anecdata that may or may not be useful - TMUX1133 gives zero charge injection with near-0V input when run with asymmetric supplies (from my notes: +3.5V and -1.4V).

Thanks for the kind words and the helpful suggestion. I will keep updating this thread as I get more results. Ultimately, I will create a github repository for the design files like I did with an AC coupled LNA, but I would like to work out more of the kinks first so that other people seeking to build one of these up aren't saddled with a bunch of troubleshooting.

Regarding the TMUX1133 charge injection, is that point the same for both source and drain charge injection? If I can solve the problem simply by varying the supplies appropriately, that would be ideal.

[Kleinstein]

The charge injection as specified for the switches is for the turn off part. This may be a bit different for the turn on part, though most of the coupling is capacitive of some kind, but possibly with some delays.
There is also simple capacitive coupling from the control signals that depends on the layout. Chances are just a manual trim for the charge injection would be good enough.

For the relay to ground the input, it is not so much about the distance, but possible shared ground and current flowing there.
It would be a good idea to have some EMI filtering at the input. Besides classic EMI it also isolates the amplifier from the source impedance, so that the source impedance has less effect on the charge injection and possibly offset. With chopper stabilized OPs the source impedance can effect both the bias and offset a little.

I totally agree that it makes sense to get the ADC running to simplifiy testing and maybe get extra data (e.g. the 2 switch settings separate).
It can also make sense to have the chopping frequency somewhat in sync with the ADC, possible leaving a short gap just after switching. A separate external DMM may not average all that well over the 2 switch settings. The ADC may be fast enough to actually do the offest correction loop also in the digital domain instead. So use ADC readings to also measure the ripple and than correct with some kind of DAC instead of U12 and fine trim the offset this way.

An interesting point to test may be the input current (e.g. with a low leakage capacitor or just a resistor).

[CurtisSeizert]

The ADC is running. I was being foiled by the fact that the STM32 hardware NCS signal goes high after each chunk of data (max 16 bits with this uC), so I implemented a software NCS signal instead and that is working. The configuration I had planned with the LTC2442 (and what I am currently running) is to use OSR=32768 as the go-to for conversion rate. With a 330 Hz clock (or odd multiples thereof to stay off powerline harmonics), any feedthrough falls in a notch of the sinc4 envelope. ADC conversions are triggered every 57 cycles of the modulator clock to keep that consistent. I attached a quick plot of a handful of values I grabbed from the serial logfile that covers maybe 50s or so. The spread is reasonably tight without having done too much work. With the ADC working, I no longer need to use one of the holes for the input terminals to feed a cable through, so I attached terminals to the front panel and will do some preliminary measurements of input bias current as well as a temperature sweep tomorrow.

The charge injection as specified for the switches is for the turn off part. This may be a bit different for the turn on part, though most of the coupling is capacitive of some kind, but possibly with some delays.
There is also simple capacitive coupling from the control signals that depends on the layout. Chances are just a manual trim for the charge injection would be good enough.

For the relay to ground the input, it is not so much about the distance, but possible shared ground and current flowing there.
It would be a good idea to have some EMI filtering at the input. Besides classic EMI it also isolates the amplifier from the source impedance, so that the source impedance has less effect on the charge injection and possibly offset. With chopper stabilized OPs the source impedance can effect both the bias and offset a little.

I totally agree that it makes sense to get the ADC running to simplifiy testing and maybe get extra data (e.g. the 2 switch settings separate).
It can also make sense to have the chopping frequency somewhat in sync with the ADC, possible leaving a short gap just after switching. A separate external DMM may not average all that well over the 2 switch settings. The ADC may be fast enough to actually do the offest correction loop also in the digital domain instead. So use ADC readings to also measure the ripple and than correct with some kind of DAC instead of U12 and fine trim the offset this way.

An interesting point to test may be the input current (e.g. with a low leakage capacitor or just a resistor).

I agree on the input filtering. Right now I just have a bead and a 10 nF cap that can be connected between the input terminals via relay. When I was designing this, I didn't think about the fact that it might be useful to measure things somewhat fast with the ADC, so I have a pair of differential inputs just connected to GND. The LTC2442 isn't all that fast, but at OSR 64 or 128 it would have been possible to get the ripple going into the filter with a 330 Hz clock. I did put a SMB jack on the board for easily measuring the output before filtering. It will be interesting to see if that residual offset is present as ripple. If it is, then it could be possible to do better with dynamic offset correction using a digital implementation of the Vos correction loop. This would be better to do with a fast(ish) ADC than the LTC2442 to make sure the spikes around the switch times aren't being averaged in. That could be pretty interesting, but I'd need to get a uC with more pins.

[Kleinstein]

I don't think it makes that much sense to look at somewhat faster ADC data to see if the chopping really works well. If there are problems / weak points I would mainly expect it at the transients and thus a thing to look at with a scope. For the ADC the question is if one wants to average over multiple whole periodes including the switching, or if one wants to skip a short time with switching. So get seprate readings for each chopper phase and have a short gap in between. With the LTC2442 the short gap is not really an option as the ADC does no look like it supports a sinc1 mode (simple integration).

Another question is than how to handle mains hum: for best suppression here one would want averaging over whole mains periods, like 10 PLC. On the other side one would also want averaging over whole periods of the chopper clock. To get both at the same time one may consider the chopper clock somewhat linked to mains. 330 Hz  as 5.5 x 60 Hz is actually not that bad in this aspect. 6 Samples per second would be 10 PLC and 55 chopper cycles.  The fitler in the ADC (seems to be sinc4) complicates thing even a bit more as one has no simple start stop of integration, but a smooth start / stop. Consecutive values are no longer independent and this complicated the noise estimates: for short times the Allan deviation curve likely looks too good. So a comparison should be based on somewhat longer time data. On the upside there can be good suppresion over larger frequency range, not just the zeros in the response and the exact timing may not be so critical.

The raw data look quite good / low noise, though it can be a bit tricky to estimate the actual noise density with somewhat correlated points.

[CurtisSeizert]

I have some data from an overnight capture of the ADC readings with the familiar cycling of the furnace on display. Unfortunately, by the time I got everything working and put back together, I didn't have the motivation to record temperature. These agree reasonably well with the data from the 3458A as a sanity check. An interesting thing from the warm-up drift is that the residual offset starts much closer to zero, and at turn on it is reasonably close to the difference in offset I get by idling the controller when debugging, this may just be coincidence, but I think it bears mention. I do believe this warmup drift is largely a thermal effect. Power cycling the meter quickly gives much less drift. This points to deficiencies in the layout with respect to minimizing the effect of parasitic thermocouples. I will ultimately get some thermal camera images of the board as it warms up to see if this highlights problem areas. The results of temperature cycling will be informative here as well - my hypothesis at this point is that the cyclic patterns in the overnight captures I have taken so far are due to changing temperature gradients on the board. This is because the shape of the time series plot looks much more like dT/dt than T.

I also attached a picture of the meter with the terminals on and everything. The rear panel battery charger and battery boards are reused from my LNA project (https://github.com/curtisseizert/LowFreqLNA/tree/main). Anecdotally, plugging in the charger doesn't disrupt the readings that much. The layout is pretty tight, but it's still delivering 2.5A from a buck converter through wires, so there is bound to be some EMI from that. In the future, I will take a capture to quantify this effect.

Here's a quick list of characterization and calibration tasks I have planned:
-Gain calibration for the +/-2mV and +/- 20mV ranges
-Vos vs source impedance (resistors with and without parallel capacitors)
-Scope capture of unfiltered input stage output
-Temperature cycling experiments

[Kleinstein]

The initial warm up drift is surprisingly fast, much faster than expected for the general temperature to stabilize on turn on.  It is considerably faster to get stable temperature gradients, especially those over shorter distances. Expecting a dT/dt part is very reasonable.

One may be able to locate sensitive areas by moving a hot probe over the PCB.

The noise performance is really good. For comparison the HP34420 specifies 8 nV_peak to peak for 50 x 10 PLC and thus some 16-20 seconds per reading.

[CurtisSeizert]

I cleaned up the schematics and fixed the errors that necessitated bodges. They are attached below.

Some very preliminary experiments gave me a sense of the input bias current, which is really more of a source impedance induced offset shift. With the input cap (10 nF, C0G) switched in, it's a bit less than 300 pA. Without the cap, it is around 1 nA. There is some potential instability with inductive sources, like op amp buffers, that I will have to look into more. Increasing the feedback capacitance is probably my first step, but a small R-C damper on the input prior to the modulator may be necessary. From my experience in stabilizing a similar input stage with more JFETs, those are the two most consequential levers to pull in such a case, but I am open to other ideas.

[NWerner]

Could you elaborate on the function of Q10/Q12? It looks like some kind of overcurrent protection  These transistors are not included in your LNA so I guess there is a very specific reason to them.

thanks in advance
Norman

[Gerhard_dk4xp]

The URL in #17:

404 - Attachment Not Found
I wanted to post here yesterday, but couldn't b/c of database error.
Sent an email to a moderator, nothing happened.

[CurtisSeizert]

Could you elaborate on the function of Q10/Q12? It looks like some kind of overcurrent protection  These transistors are not included in your LNA so I guess there is a very specific reason to them.

thanks in advance
Norman

These are "transconductance enhancers" (See AoE Ch. 3x.4). The goal here is to increase the diff pair transconductance and gain as much as possible while keeping the loop stable. This is necessary to ensure low offset and drift because the Vos of the ADA4625-1 is not modulated up to the MOD_CLK frequency. As such, the whole offset correction block serves only to attenuate the offset and drift of the ADA4625-1 by a factor of the differential gain of the diff pair. The emitter resistors R32 and R44 are necessary to reduce the gain enough to keep the loop stable. This is also the case with R77 and C118 in the G=101 configuration - the closed loop gain needs to be around 60dB at high frequencies to keep oscillations at bay.

[CurtisSeizert]

I began looking into the impact of modulator frequency on noise and residual offset yesterday in a more systematic way than I had done before. I wrote the code to change the TIM2 counter (when this overflows, it triggers an interrupt - the ADC read is in the ISR) to automatically give the greatest throughput while maintaining an integer number of modulator clock cycles per ADC read. In practice, this gave sample frequencies between 5.69 and 5.879 SPS (5.88 SPS is the maximum read rate of the converter at OSR=32768). I updated the code, and waited for the output to settle for each experiment. Once it looked settled, I pasted the PuTTY scrollback into Excel and checked that it had indeed settled. My criterion for valid data here was abs(first reading - last reading) < 2 sigma, and if that wasn't met, I let it go a bit longer and repeated. It's not ideal, but it's good enough for a forum post.

The two responses I analyzed were residual Vos, which followed a predictable pattern, and noise density. I calculated noise density as sigma/sqrt(bandwidth), which assumes it is white noise. The denominator in all cases is nearly identical, so this is really a surrogate for standard deviation, but it is scaled such that it permits comparison to previous data I had gathered. The key previous data point here is that noise density, as measured post-Butterworth filter on a DMM, was about 1.15 nV/rtHz at a 330 Hz modulator clock frequency. I chose this frequency because it is the least common multiple of 55 Hz (the first sinc4 notch frequency for OSR=32768) and 30 Hz. Here's the data from the ADC:

Freq       Mean  Noise density
149.97   0.43   1.19
149.97   0.42   1.20
165.02   0.42   2.29
180.01   0.42   2.77
210.00   0.42   1.71
330.03   0.43   1.84
330.03   0.42   1.74
990.10   0.46   1.68
2490.04   0.52   1.74
9900.99   0.82   2.17
15151.52   1.04   2.51

Frequency is in Hz, mean is in uV, and noise density is in nV/rtHz. The data are also summarized in the attached graph. The 150 Hz and 330 Hz points were repeated. The order wasn't random, but it wasn't by frequency. The two 150 Hz experiments were actually the first and last runs to control for drift.

It is not clear to me why the ADC noise is so much worse than the DMM sampling at about the same rate for my standard 330 Hz modulator frequency, and I'll investigate this further by getting a spectrum at some of the key points here. The lack of impact on Vos at powerline harmonics (180 Hz) vs between them (such as 150 Hz and 210 Hz) was expected from understanding how the offset correction loop works and simulation. Signals around the modulator frequency lead to an offset between the two inputs of the differential pair (though the frequency response of the HP filters and integrators in the Vos correction loop are meant to minimize this), but this offset is modulated up to the modulator frequency, so it does not appear as a DC offset at the output. This is probably the reason why the noise density with a 180 Hz clock is so much higher - increased ripple at the clock frequency. It may be useful to implement a synchronous filter in a later revision to better reject this ripple. That said, the anomaly at 330 Hz (wrt to DMM results) means some caution might be warranted in interpreting the calculated noise densities here; there could be other factors at play. Anyways, the absence of rectification of signals that are coherent with the clock frequency is one of the useful features of this topology. This makes it less sensitive to crosstalk from the clock lines, at least with respect to offset. Coherent signals that are modulated faster than the settling time of the filter will cause problems, but this could also be solved by adding a synchronous filter.

Having gotten what I thought was an optimum clock frequency for measuring drift, etc. with a minimum of noise, I put the box into a thermal chamber, but I found the loop was not stable when clocked at 150 Hz, especially in the temperature chamber (for some reason). This happened a few times. The Vos would settle then slowly drift up before shooting up to about 16 uV (always about the same value). On occasion, it would jump around a bit and then settle back to a reasonably close Vos with a lot more noise. I checked what had happened, and the CM of the Vos correction diff pair had gone low enough to bring the current sink transistor into saturation. To see if it would fix the issue, I put a 10M resistor in parallel with one of the integrator caps (just one so as not to reduce the gain of the Vos correction loop). I took the opportunity to increase the FB caps to 33 pF. These changes made it more likely to settle back from 16 uV to something different at higher noise, but they didn't prevent the issue. Interestingly, it was stable on the bench at this frequency but not in the thermal chamber. Going back to 330 Hz was necessary to keep everything stable. I attached a plot of this divergence, but I reduced the scale so the increased noise would be apparent.

Edit: Credit to Kleinstein for pointing out the potential CM issue associated with the NPN diff pair.

[Kleinstein]

The type of filter at the ADC can make a difference for the noise. The LTC2442 has a noise BW of some 6 Hz when used with 6 SPS. Classical integration with a SIN1 response would be only 3 Hz BW for 6 SPS. depending on how the DMM is used (in simple AZ mode on most HP meters) it could however also be 6 Hz.

So the LTC2442 may not be such a good choice for the ADC. From the description it looks like the ADC reverses polarity internally for every conversion and thus has to wait for internal settling of the fitler. This gives the extra noise density from uneven weight to different times.  It may still work if there is some analog filtering and than using a rather fast ADC conversion rate and more averaging on the µC side.
Ideally one would like an ADC with minimal bandwidt and this no latency (sinc1 response) and conversions in sync with the chopper. Instead of very slow conversions this could also be fast ones, so that the ADC could measure the 2 switch settings separately and if needed skip the switching glitch part, effectively adding dead time.

[CurtisSeizert]

The type of filter at the ADC can make a difference for the noise. The LTC2442 has a noise BW of some 6 Hz when used with 6 SPS. Classical integration with a SIN1 response would be only 3 Hz BW for 6 SPS. depending on how the DMM is used (in simple AZ mode on most HP meters) it could however also be 6 Hz.

So the LTC2442 may not be such a good choice for the ADC. From the description it looks like the ADC reverses polarity internally for every conversion and thus has to wait for internal settling of the fitler. This gives the extra noise density from uneven weight to different times.  It may still work if there is some analog filtering and than using a rather fast ADC conversion rate and more averaging on the µC side.
Ideally one would like an ADC with minimal bandwidt and this no latency (sinc1 response) and conversions in sync with the chopper. Instead of very slow conversions this could also be fast ones, so that the ADC could measure the 2 switch settings separately and if needed skip the switching glitch part, effectively adding dead time.

It seems like it uses CDS to correct its offset. I had originally thought it was autozeroing because the noise density was close to 1.4 * the DMM measurement. You can get the sampling frequency to be better using the "TWOX" register, which gives a latency of one reading but doubles the throughput. However, it does not look like you can take advantage of this doubled sampling frequency unless you drive the oscillator from an external source; in my design I am using the internal oscillator. It does not mention this in the datasheet except that it does not give different values for SPS with and without TWOX when using the internal oscillator. The thing is, when I calculated the noise densities, the numbers I was dividing by were very close to the (square root of the) ENBW listed in the datasheet, so it is not clear that this could be the source of the discrepancy between the ADC and DMM noise values. It is also not clear why this would be significantly affected by the modulator clock, which should be attenuated by >60 dB for all cases based on the filter envelope with OSR=32768. Hopefully I can find a satisfactory answer to these questions, but I am beginning to agree with you that the LTC2442 could be improved. I do like it for proof of concept, nonetheless, because it is very easy to use. I think maybe the AD4032-24 would be a good choice for this application due to its very modest current consumption and good accuracy. I figure it would cost about 1 mA (2 x ADA4805) to drive it relative to the LTC2442. I would like to use something like the AD4134, but it is waay too thirsty.

[Kleinstein]

A way around the extra noise BW from the ADC / DMM can be some analog low pass with a BW of some 10-30 Hz and than using the ADC with a significant higher speed (e.g. 300 SPS). This would however likely mean not getting the 50/60 Hz suppression from the ADC. Alternatively one would need a rather low analog BW. To get good 50/60 Hz suppression with a low ENBW fitler one may need a more accurate external clock. The relatively wide notch comes with the added noise BW.

A fast ADC like the AD4030 comes with it's own can of worms. They need good drivers for the signal and reference. Poor drivers can effect the INL - so the good INL specs depend on the circuit around. The drivers will add quite a bit to the power consumption. The other point is that there will be more EMI from faster and more SPI trafic and the µC is also more buissy. One the upside a faster ADC may allow to use the amplifier in a non chopped mode (if the ripple suppresson part can be switched passive, e.g. easy with the DAC based version) for somewhat faster signals and to add a dead time in the digital domain.

Before thinking more about another ADC one should look at the switching transients with a scope.