More voltage references - die pictures

[UnijunctionTransistor]

As always, your images and detailed descriptions are a welcome addition to any EEVBLOG section.

[Noopy]

Thank you! I´m happy to hear that.
...and I still have so many party and pictures here... 

[AnalogTodd]

There are some chips out there that you can feed in a new configuration after blowing the lockout if you know the proper programming sequence (it's a way to check things later if you want)

Could you please explain how opamps and voltage references are trimmed after packaging? Because there are no programming pins (except some rare cases, I assume do-not-connect and not-connected pins are used for that). So, I guess, somehow output and power pins are used? Because using input pins, I think, may compromise opamp performance (input impedance, capacitance, crosstalk...).

The TI opamps are programmed through the output. As far as I know they switch a V+ or a V- to the output.

Storing the data in fuses which are read by an additional circuit can be problematic. At work we accidently found a way to disturb the startup of a voltage regulator. Sometimes it switched to another output voltage.  It´s really a pain to find such a problem since in the first place you don´t know that the voltage regulator can be configured.

Post-package trim is usually something that we pay very careful attention to, we don't want a situation like you ran into to be found. We work to make sure nothing loads until input voltages are high enough for the read circuitry and the logic to be reliable. Of course, I can only speak for the few places I have worked, not for every company out there.

The way we often do it is to use one pin or a combination of pins to feed digital data in to the trim network from the ATE system. A common thing we would do is to have a pin that could be pulled to a voltage outside its normal operating range to put the part into 'trim mode'. From there, sometimes we have used specific pulse widths to signify a zero or one, or different levels outside the normal range (sometimes done with currents, other times voltages). Something like this reference may go into trim mode if the EN pin was pulled above VIN by a certain amount (often violating the ABS MAX rating shown on the data sheet), making the output go high impedance and allowing you to feed data in through that pin.

Depending on how it gets done, sometimes a digital code sequence (basically a password) needs to be fed in to put things in trim mode to prevent unwanted access. There's a lot that designers can do to protect against someone unwittingly getting the part into trim mode, and good designers work with their teams to make things as bulletproof as possible.

[EC8010]

I'd like to formally second my thanks for your valuable contributions. I'm seriously impressed by the quality of your photographs, but even more by your lucid interpretations of what you see. Much of what you describe at the silicon level is over my head, but that doesn't matter; one day I may have more knowledge and be able to come back and understand more.

[floobydust]

I do chip design myself [...]

Can you comment on the recovery time (mechanism) for heated voltage references.
Example: "It needed around 1kHr to get back to the same level as before the 1 week power off." post
I am curious what takes so long to settle within the die.

Not that I am a fan of the push to SMT packaging, and outsourcing fab for the high dollar references. Linear Tech Milpitas fab huge loss I think.

[Noopy]

Post-package trim is usually something that we pay very careful attention to, we don't want a situation like you ran into to be found. We work to make sure nothing loads until input voltages are high enough for the read circuitry and the logic to be reliable. Of course, I can only speak for the few places I have worked, not for every company out there.

I have to say that it was like a side channel attack:
The circuit around the voltage regulator was bad. It toggled the Enable-Pin very fast around the startup. The interal circuit tried to read the fuse but the logic above this circuit didn´t wait for the result and took the default value.
Nevertheless, it was a very interesting problem. 

I'd like to formally second my thanks for your valuable contributions. I'm seriously impressed by the quality of your photographs, but even more by your lucid interpretations of what you see. Much of what you describe at the silicon level is over my head, but that doesn't matter; one day I may have more knowledge and be able to come back and understand more.

Thank you too. I´m doing my very best. 

[AnalogTodd]

I do chip design myself [...]

Can you comment on the recovery time (mechanism) for heated voltage references.
Example: "It needed around 1kHr to get back to the same level as before the 1 week power off." post
I am curious what takes so long to settle within the die.

Not that I am a fan of the push to SMT packaging, and outsourcing fab for the high dollar references. Linear Tech Milpitas fab huge loss I think.

There are some really strange effects that can come into play when it comes to packaging. One of the most recent ones I ran into was doing 1kHr at 125C on a part and having the internal reference shift and then later finding that an hour at 150C would reset the shift back. What was most strange about this was it was in a hermetic package (like the ADR1001), so no mold compound in contact with the die and no possible situation like mobile ion or anything. Turned out that the die attach material at 125C would build up stress in it that caused the shift and when you took the part up to 150C it went past the glassivation temperature of the die attach, allowing the stress to dissipate. This may be a similar effect that was seen by Andreas--some stress was building in the die attach and it maintained with the part on and the heated die. Power down for a week and some of that dissipates.

There's a lot to think about when it comes to top notch analog design. The circuit design itself is only the beginning. Next up is layout and considering thermal effects and die stresses. Then you have to think about the packaging and testing. The leadframe can be Kovar (steel) or copper depending on what you need and die attach can be changed as well. Kovar is nice because it has the same temperature expansion as silicon, but it sucks for heat transfer (where copper is a lot better). For die attach, do you need it to be electrically conductive? Good thermal conductivity (some are better at transient thermals than others)? Low stress? Now see if you're going to go into a molded package. The mold compound ends up with various grain sizes in it so you get differential stress on areas of the die. That can be mitigated by adding a layer like polyimide on the die. Finally, figure out how to test parts. Make sure you have Kelvin connections for critical points!

I will agree with you on the loss that was the closing of LTC's Milpitas fab after the acquisition by ADI. With the fab close by, we had access to our process engineers and could work side-by-side with them developing new devices and bringing new processes up. Having your own fab allows you to do custom processes that gave optimal results for high-end analog designs. Need bipolar devices to have high beta and still have the process give you good CMOS and DMOS? That can be done. I got to suit up more than once and see the inside of the fab, and not just the operator side but also the back side where you can see the quartz furnace tubes and equipment that is usually hidden. Great experience.

Post-package trim is usually something that we pay very careful attention to, we don't want a situation like you ran into to be found. We work to make sure nothing loads until input voltages are high enough for the read circuitry and the logic to be reliable. Of course, I can only speak for the few places I have worked, not for every company out there.

I have to say that it was like a side channel attack:
The circuit around the voltage regulator was bad. It toggled the Enable-Pin very fast around the startup. The interal circuit tried to read the fuse but the logic above this circuit didn´t wait for the result and took the default value.
Nevertheless, it was a very interesting problem. 

That's a poor design. When you have internal trims like this you set up the logic to read the trims and hold everything else off until those are read and loaded. If you try to start everything up before you have loaded your trim values you can see the exact same situation you did.

[Andreas]

1kHr to get back to the same level as before the 1 week power off." post
I am curious what takes so long to settle within the die.

Hello,
there are 2 possible suspects:
a) the die attach (see answer from Todd)
b) the effect of humidity of the epoxy PCB creating stress to the SMD package.
   (when heated the PCB gets dry and shrinks
    in off state the epoxy gets more humide from air humidity and expands
    in on state again the epoxy dries and shrinks again
   usually you have time constants of several days to ~1 week for this effect with epoxy)

with best regards

Andreas

[iMo]

I do chip design myself [...]

Can you comment on the recovery time (mechanism) for heated voltage references.
Example: "It needed around 1kHr to get back to the same level as before the 1 week power off." post
I am curious what takes so long to settle within the die..

In my "trampoline" mounting style I had not observed such a hysteresis. So it most probably comes from by the pcb induced stress (which might be rather large with such package). I estimate the temperature differences at the pcb some 20-30C when the chip is on/off..

[Noopy]

I have to say that it was like a side channel attack:
The circuit around the voltage regulator was bad. It toggled the Enable-Pin very fast around the startup. The interal circuit tried to read the fuse but the logic above this circuit didn´t wait for the result and took the default value.
Nevertheless, it was a very interesting problem. 

That's a poor design. When you have internal trims like this you set up the logic to read the trims and hold everything else off until those are read and loaded. If you try to start everything up before you have loaded your trim values you can see the exact same situation you did.

There was a deadtime circuit which should guarantee that there is enough time between reading the fuse and doing the configuration of the rest of the circuit. But it was like a RC circuit. If you switch the circuit off and on very fast the circuit will skip the deadtime because the capacitor is still charged. 

[Noopy]

The ADR3625 is a voltage reference with an output voltage of 2,5V. The ADR3630 (3V) and ADR3650 (5V) belong to the same family. The maximum current consumption is 90µA. The ADR3625 can source up to 70mA and sink up to 20mA. Analog Devices sells an A-grade and a B-grade. Unusually, the output voltage of the B-grade has the lower initial error with a maximum of 0,04%. The output voltage noise is specified as 7,5µVpp. The typical temperature drift is 2ppm/°C. With the A-grade, the value remains well below 3ppm/°C.




The datasheet contains a block diagram. It is very similar to the block diagram of the ADR3525. The only difference is that a large number of protection diodes have been added. While the ADR3525 datasheet refers to a special operating mode of the bandgap reference, there is no mention of this technology in the ADR3625 datasheet.




The die of the ADR3625 measures 2,20mm x 1,55mm, making it significantly larger than the die of the ADR3525.

This image is also available in a higher resolution: https://www.richis-lab.de/images/REF01/54x03XL.jpg (37 MB)




The design dates back to 2020. BV most likely stands for Beaverton, an American location of Analog Devices. The full designation ADR3625 is shown here. This could mean that the various output voltages are set via the metal layer. However, it is equally conceivable that the present design can represent all three output voltages and will be configured appropriately after production. REV-F shows that the circuit has been revised several times.

The letters and numbers are all connected to each other and even contact a deeper layer in the lower right area. This ensures that no errors occur due to electrically isolated islands during automated design checks.




The circuit is quite complex and therefore cannot be analyzed in detail. However, it appears to be fundamentally different in design from the circuit in the ADR3525. The most striking feature is the output stage, which has been divided into two blocks. These blocks have been placed on the left and right edges. Due to the high output power of the ADR3625, a lot of power loss can occur in the output stages. By placing them on both edges, they heat up the die more evenly.




The ADR3625 datasheet mentions that it is configured using the DigiTrim process at the end of production. In the vertically arranged block shown here, you can see the circuit components of 25 fuses. To the left of this is certainly the control logic for this configuration option. The large horizontal block at the bottom edge appears to contain 32 switchable current sinks, thus representing a type of DAC. However, control lines to various other circuits can also be seen.




The circuit block with the fuses is reminiscent of the integrated circuit in the ADR3525, but is not completely identical to it.


https://www.richis-lab.de/REF49.htm

 

[floobydust]

Does DigiTrim use memory cells? I couldn't find the patent.

"Digital control of adjustment currents through logic circuits and weighted current sources."

"DigiTrim adjusts circuit performance by programming digitally weighted current sources. In this patented new trim method, the trim information is entered through existing analog pins using a special digital keyword sequence. The adjustment values can be temporarily programmed, evaluated and readjusted for optimum accuracy before permanent adjustment is performed. After the trim is completed, the trim circuit is locked out to prevent the possibility of any accidental re-trimming by the end user.

The physical trimming, achieved by blowing polysilicon fuses, is very reliable. No extra pads or pins are required for this trim method and no special test equipment is needed to perform the trimming. The trims can be done after packaging so that assembly related shifts may be eliminated. No testing is required at the wafer level assuming reasonable die yields. No special wafer fabrication process is required and circuits can even be produced by our foundry partners. All of the trim circuitry scales with the process features so that as the process and the amplifier circuit shrink, the trim circuit also shrinks proportionally. The trim circuits are considerably smaller than normal amplifier circuits so that they contribute minimally to die cost. The trims are discrete as in link trimming and zener zapping but the required accuracy is easily achieved at a very small cost increase over an untrimmed part.

The first part to use this new scheme is Analog Devices AD8602 dual, low cost, rail-to-rail CMOS amplifier. The offset voltage is trimmed for both high and low common-mode voltage conditions so that the offset voltage is under 500 µV over the full common mode input voltage range. With a bandwidth of 8MHz, slew rate of 5V/µS and current consumption of only 640 µA per amplifier, this part will support a variety of high volume, cost sensitive applications from bar-code scanners to GSM phones.

The DigiTrim approach could also support user trimming of system offsets with a different amplifier design."

[Noopy]

I haven´t found very much information about the DigiTrim technology either.

Reading what is public shows us they use polysilicon fuses. Whether there are additional volatile memory cells is not clear. But it would make sense because I assume it´s easier (faster) to tune the correction values when you can toggle the bits more than once. Time is money.
In my view the circuit around the fuse is big enough to contain one volatile memory cell for each fuse.

[AnalogTodd]

These trim methods use volatile memory cells that get loaded with the states of the fuses and are fed into a DAC upon power-up. It doesn't take anything more than a simple flip-flop to hold the value; you only load the fuse states once on each power-up and don't care if those lose the information on power-down. Next power-up they will reload.

The time is spent in the ATE to go through and trim parts after assembly. Trimming at wafer sort requires as much time (or more) as post-assembly trimming and you widen your distribution if you trim at wafer sort because of stresses involved in packaging. Wafer sort now becomes a simple functional test (which is quick) and the digital logic inside the chip gives you fairly fast tuning of critical parameters at final test. The way it often gets done is to make a measurement or two, load a first "guess" into the volatile memory, then see the result. From there, it doesn't take a lot of additional time to try several of the trim codes around that guess point to find the best one. Once it's known what the best codes are, the associated fuses can be blown and finally the chip can have the trimming locked down.

Yes, time is money for all of this. But the tradeoff is that you can spend an extra penny or two in ATE time to get a part with better specs that can be sold for an extra five or ten cents.

The old metal fuses could not be done in a molded package. Zener zaps required significant current and voltage. Laser trim had to be done at wafer sort and was very slow (not to mention adding extra process steps). This method of post-package trim gives a better product at a cost of the die area for the digital logic.

The interesting thing about all of this loading of fuse states into memory is that you don't need to simply restrict yourself to trimming analog circuits. I've seen serial numbers locked into chips to track trim values from one test point to another, not locking down final trim values until the last test point was done. Saving that data together with the lot codes meant any returns from customers could be looked up to review individual part test results before sale.

[daqq]

You know, it's funny when you think about it - until they break it they have a decent little DAC with a built-in reference

[iMo]

..The old metal fuses could not be done in a molded package. Zener zaps required significant current and voltage..

In the LT1021 thread I experimented with blowing up its fuses and I reported the chips stopped working after some time after blowing the fuses up.. Like the pressure and shrapnels creating during the "explosion" of the fuses affected the die somehow.

PS: might it be the flash mem cells are used for storing the DAC settings?

[Kleinstein]

You know, it's funny when you think about it - until they break it they have a decent little DAC with a built-in reference

The DAC for T-trim often only needs a small range (e.g. 6 bits) and does not need good DNL. Depending on the trim range it may still need good stability.

[AnalogTodd]

..The old metal fuses could not be done in a molded package. Zener zaps required significant current and voltage..

In the LT1021 thread I experimented with blowing up its fuses and I reported the chips stopped working after some time after blowing the fuses up.. Like the pressure and shrapnels creating during the "explosion" of the fuses affected the die somehow.

PS: might it be the flash mem cells are used for storing the DAC settings?

If you go and look through a lot of the different die pictures that Noopy has posted over the years, you'll find ones with metal fuse links. All of these will have one thing in common, which is openings in the passivation over the fuses. When blowing a fuse, ideally the blowing does not cause the metal to shrapnel out--that actually can cause trouble with wafer sort probes over time as the metal will land on them and build up. Instead, the idea is that you want to heat the metal to the point that it separates in the center and the molten metal peels back to create a nice open space between with clean globules of metal at each end. In a molded package, there really isn't a place for that to happen and the addition of the mold compound also acts as a heat sink requiring higher current to blow the fuse. Of course, the metal is resistive, so it takes higher voltage to get to that current, and once you open the metal your wires to the blowing points may give an inductive kick that can over-voltage circuit internals (we always had zener diodes close by to mitigate that). There's a myriad of reasons that your experience ended up with chips failing.

We never used flash memory cells for storing the DAC settings. Flash memory needs higher voltages to program that can be beyond process capabilities and it is only guaranteed for a certain number of cycles. Fuses can be blown at voltages that the process can handle and all of the work done over the years has found them to be quite permanent. The fuses are considered the read-only memory for what the DAC settings need to be (after trim).

You know, it's funny when you think about it - until they break it they have a decent little DAC with a built-in reference

The DAC for T-trim often only needs a small range (e.g. 6 bits) and does not need good DNL. Depending on the trim range it may still need good stability.

You're correct about the DAC--it's not something that a lot of time and effort is used for the design of it. Even when you want more bits, the nice thing is that you don't have to have everything perfectly dialed for things like INL or DNL. You can get start by getting close to the final value and then check nearby codes to tweak for best results. As for the stability of it, all we usually do is open or close switches to change impedances or add/subtract currents, the stability of the DAC isn't usually the concern as much as the loop you're trying to adjust.