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#50 Reply
Posted by
Kleinstein
on 24 Sep, 2021 17:20
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Requiring only low frequency noise in the 0.1 to 10 Hz range is a bit untypical for a nV meter. The more practical requirement for a DC nV meter is to have low noise also at lower frequencies. The 1 to 10 Hz range one the other hand is not as interesting.
I point not mentioned in the challange but also important is some tolerance to external EMI. I just had an example where extanal EMI caused an relatable 4 µV offset shift. It still is hard to quantify.
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#51 Reply
Posted by
TiN
on 25 Sep, 2021 00:43
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Good start. Regarding noise it was not expanded into full specified bandwidths and levels on purpose, to let designer choose the fitting / preferred design and topology. 0.1-10Hz levels put there so we can have a "common ground" to compare different designs and approaches. I've overspecified interfaces enough already to get hate letters about abandoning holy RS232, so enough of that for one contest
To reiterate again : key goal of this challenge is for people to have fun building difficult mixed signal project, learn about microvolts and nanovolts and share the findings. Goal is NOT building commercial alternative for fully characterized and specified nanovoltmeter.
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For the nV experts here: Is there an advantage in using a fully differential design, like ferret_guy's with instrumentation amplifiers, vs. just using single ended design with floating ground? It would improve high frequency noise rejection perhaps? Does any commercial meter use this approach?
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#53 Reply
Posted by
ferret_guy
on 25 Sep, 2021 02:57
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To be clear my design could be fully differential, but it is not. The negative input is tied hard to GND. If you have a fully differential design then you need to stay within the CM range of the in-amps which will limit the input range.
The in-amps I use have a unique architecture that makes their CM range almost rail to rail.
When designing the system and looking at the differences between differential and single-ended design I didn't really find a significant difference between the two from a noise/offset perspective.
However, I found that the available in-amps had a little bit lower noise than op-amps, especially when factoring in the noise of the feedback networks; even with optimal distribution of gain between several stages.
PS: It seems that TI does not include 0-10Hz noise as a standard spec which is annoying. Looking at their datasheets it looks like their 1/f noise extends to a much higher frequency than for AD parts; which is interesting.
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#54 Reply
Posted by
razvan784
on 26 Sep, 2021 09:16
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One possible problem with the AD8428 is its 50 nA input current, that's 400 nA worst-case for 8 in parallel. Let's say you get lucky and only have 100 nA too keep calculations simple. This is perfectly fine for measuring shorts, thermocouples, and differences between voltage references that have low output impedance. But what if you want to measure say, a 10 ohm current shunt? Now you have a 1 uV offset that's outside the autozero loop. Sure, you can compensate it in software. But what if you want to compare two groups of 4 Vrefs each that are averaged with resistors and have a 100 ohm output impedance? This is a reasonable application for a nV meter. Now you have 10 microvolts error (10% full-scale on the lowest range) which is outside the autozero loop and you might not even notice is there!
That's why I would target an input current of a few nA at most, which means a FET input stage.
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#55 Reply
Posted by
Kleinstein
on 26 Sep, 2021 10:53
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For a practical solution the AD8428 may not be the best way, due to the high bias curret. However by the letters of the challange it is a possible way to meet the 30 nV_pp noise goal. One can compensate the bias current with an added current source in hardware too. This is done with some older DMMs, like Datron 1061, that used a BJT based input stage.
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#56 Reply
Posted by
ferret_guy
on 26 Sep, 2021 16:01
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If you look at figure 6 the mean input bias current is. -10.8nA. I only expect to use around 4 of them giving an average input bias of around 40nA which I agree is not great.
I hadn't even considered the idea of compensating the input bias current. The input offset current is very low, if I used feedback to compensate for the input bias based on the bias flowing in/out of the - input then sub nA bias currents are achievable.
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#57 Reply
Posted by
KT88
on 26 Sep, 2021 17:06
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A differential input may have some advantages: the GND could be tied to a guard while the positive and negative input can be kept perfectly symmetrical. This helps a lot with keeping thermal EMF at a minimum.
I would put a pair of AZ amps in front of the INAmp (e.g. AD8428). The circuit would look like the first stage of the AD8428 with a gain in the ballpark x10 using the ADA4523 or ADA4522. Maybe even in parallel (like MarcoReps in his LNA design). Two would give 3dB and 4 would give 6dB of noise reduction...
Cheers
Andreas
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#58 Reply
Posted by
Kleinstein
on 26 Sep, 2021 17:25
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To get to the required noise level (e.g. some 1.5 nV /sqrt(Hz)) it would take something like 8 of the ADA4523 in parallel, if there are no additional noise sources. The protection, input filtering and switching will likely add some noise, and thus leave even less noise budget for the amplifier. This may be feasable in a kind of brute force way, but still with some challanges (e.g. interference between the chips).
The AD8428 is lower noise to start with and could get away with fewer chips to start with. However it has more 1/f noise and may thus need some extra chopping for a more real world use.
With an unknown source resistance the relvant current is the bias current (one input current) and no the offset (difference between input). The offset can become relevant if chopping is used to swap the inputs.
Analog compensation needs a trim step and a large resistor (e.g. 100 M range), but is otherwise not too difficult if the bias is stable and does not drift much (e.g. with temperature, or input capacitance as with some AZ OPs).
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#59 Reply
Posted by
KT88
on 26 Sep, 2021 18:17
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A bipolar, non-AZ amp like the AD8428 is usually great at voltage noise above 0.1 - 1kHz. But 1/f noise and current noise doesn't work well if the source resisitance is not extremely low and DC performance is the major concern.
Once the source resisitance gets significantly higher than a few Ohms for DC the AZ amp wins big time.
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#60 Reply
Posted by
bobAk
on 26 Sep, 2021 18:18
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Simple op amp based nanovoltmeter connected in parallel to reduce noise and chopping. The article can be easily translated through goolge translator.
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As long as one uses a BJT input stage chip, then LT6018 is probably the best and can achieve required 0.1-10Hz nVpp noise without averaging. But for cases of significant input resistance it would be better to have a JFET input stage, in which case one probably has to go to discrete input transistors as in 34420.
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#62 Reply
Posted by
Kleinstein
on 26 Sep, 2021 19:21
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The 34420 does it a bit the hard way: 50% the time reading the actual input signal and 50% of the time reading zero and than taking the difference. So the input is only ready half the time.
A full wave chapper can switch between the input signal and the inverted input signal. So one could do this a little faster. Especially for small signals one can switch faster than the 34420 does - this reduces the 1/f noise.
TI just introduced some new JFETs with pretty impressive low frequency noise. Not enough to get to the targe directly, but still good for JFETs.
So one could use a chopper with relatively low switching frequency. So that the switching glitches get less important.
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#63 Reply
Posted by
jbb
on 14 Oct, 2021 22:49
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I don’t have the time to enter, but I have been thinking about the low noise target.
TiN’s initial benchmark is 120nV pk-pk over 0.1-10Hz.
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Thought A: low frequency chopper
Estimate RMS noise = pk-pk / 6.6, we get 18nV RMS
Equivalent noise BW = 1.6 * 10 = 16 Hz
Allowable noise: 18/sqrt(16) = 4.5nV / sqrt(Hz)
For low input current, use something like TI JFE2140 for first gain stage (1.4nV /sqrt(Hz) for pair and 20pA Ibias). Chopper frequency would need to be low to keep the switched capacitor current low.
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Thought B: direct amplifier
JFE2140 rated for 120nV pk-pk typical over 0.1-10Hz. (At id = 2mA, gm=10mA/V.) Part binning might be required.
But there are 2 in a diff amp, so multiply by sqrt(2). That takes us over limit, so parallel 3 stages for 120*sqrt(2/3) = approx 100nV
That leaves us some 66 nV pk-pk or 10 nV/sqrt(Hz) for everything else.
Estimate RMS noise = pk-pk / 6.6, we get 10nV RMS.
Equivalent noise BW = 1.6 * 10 = 16 Hz
Allowable noise: 10/sqrt(16) = 2.5nV / sqrt(Hz)
Assuming around 150 R (1.55nV/rtHz) for input protection (and matching feedback divider) leaves 1.2nV/rtHz for everything else, referred to input.
Given gm = 30mA/V, a 1k drain resistor and differential signal collection I think the JFET stage would have a gain of around 60V/V. Being pessimistic I’ll halve that to 30V/V. Therefore the 1.2nV/rtHz coverts to 36nV/rtHz after JFET gain. Now to see what I can get in the way of opamps… the opamp 1/f noise could be an issue.
A big factor to consider is the temperature drift below 0.1Hz. Has anyone tried ovenized JFETs before for constant temperature? I was thinking a 45 deg C oven might work, and one could put the voltage reference in there too.
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#64 Reply
Posted by
branadic
on 15 Oct, 2021 06:24
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#65 Reply
Posted by
Kleinstein
on 15 Oct, 2021 06:35
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Temperature stabilized FETs have been done.
I think the target is 30 nV_pp, not 120 nV_pp. So the required noise level is a little lower. This would be out of reach for the usual JFET amplifiers, unless using massive parallel (not 3, but more like 50 units). It may just work with paralleled BJT based amplifiers at a cost of higher input current. This may not be very practical, but still fit the listed targets.
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#66 Reply
Posted by
dietert1
on 15 Oct, 2021 08:11
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Can somebody explain why one would not use an OPA140 instead of a JFE2140? Input noise spec in 0.1 to 10 Hz is the same. Why recommending discrete again and again?
Regards, Dieter
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#67 Reply
Posted by
Kleinstein
on 15 Oct, 2021 09:21
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The OPA140 noise specs are a bit higher than the JFE2140. (5 nV/sqrt(hz) and 250 nV_pp compared to some 1.4 and 130 nV for the JFET2140 - with the extra factor 1.4 for 2 FETs). The discrete JFET seems to be larger area (estimated 4 x) and can use more current than the OPs input stage.
The main use for the discrete JFETs would be when one really needs the lowest noise in combination with low input bias. This could be even for a more electrometer like application with selected ones or a tuned votlage to get very low input current, below 1 pA.
For chopper amplifier with usually higher frequenies (like 100 Hz) the JFE2140 is not that special. At 1 kHz there are several JFETs with comparable noise level. The special point is the low noise also at low frequencies (e.g. 10 Hz).
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#68 Reply
Posted by
dietert1
on 15 Oct, 2021 12:30
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When i look at the paper branadic linked, peak to peak voltage noise of the discrete FET amplifier is 220 to 250 nV again (Fig. 5 a). So even with all the fuss of amplifier adjustment and TEC temperature stabilization, the result with the discrete amplifier isn't lower noise. You can't just look of the FET at the specs, noise will add up.
Much easier to wire up an OPA140 instead of building the discrete amplifier in that paper. And with a OPA4140 noise can be about 2x lower.
Regards, Dieter
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#69 Reply
Posted by
Kleinstein
on 15 Oct, 2021 13:41
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The figure 5 in the xrxiv,org paper has the time axis in days, not seconds. So this is some 250 nV_pp for 5 days to 10 Hz.
The 0.1-10 Hz number is given in the text, with 4,7 nV_rms which would be around 30 nV_pp - just the number that TiN wanted for the nV meter.
If done right the noise of the differential amplifier with 2 JFETs will be mainly the noise of the 2 JFETs. The other conribution can be kept small, especially if there is no need for source resistors to compensate a large mismatch. So if done right with JFE2140, one could get a noise in the 140 nV_pp (0.1 to 10 Hz) range. That is significant lower than the OPA140 noise, more like the noise from the 4 units in the OPA4140 combinted.
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#70 Reply
Posted by
branadic
on 15 Oct, 2021 16:15
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#71 Reply
Posted by
macaba
on 15 Oct, 2021 16:23
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In addition to what kleinstein said, you’d need around 70 OPA140 channels to get a low enough noise for this competition without chopping. That results in around 490pF of input capacitance. When you go discrete with good cascode, as per the paper, that capacitance is severely reduced. The IF3602 300pF goes down to 10pF if the paper is to be believed.
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#72 Reply
Posted by
macaba
on 15 Oct, 2021 16:27
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sceptical with the price of IF3602
I’ve come to the conclusion, as others probably have, that by the time you parallel a load of cheap JFETs to get similar performance, the price starts getting near the IF3602. Add to that the time required for matching, and the board space for all these parts, the IF3602 starts looking very good.
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#73 Reply
Posted by
branadic
on 15 Oct, 2021 21:28
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You can get matched pairs of 2SK170 for a small doller on ebay, while CPH3910 is quite cheap available at Mouser. Also MMBF5103 is available cheap. Some people are also lucky to have BF862 in stock, so do I
Unfortunately, some of the really interesting FETs are obsolete these days, such as 2N5564/NPD5564 or BF862, but I'm sure one or the other guy does have some of them in the drawer.
-branadic-
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#74 Reply
Posted by
Kleinstein
on 16 Oct, 2021 09:59
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For the with a chopper in front the requirements for the amplifier are less stringent. The target than would be more like 0.7-1 nV/sqrt(Hz) at some 1 kHz. There are a few FETs to choose from and one can get away without good matching and possibly even with just 1 pair.
The amplifier gets even less demangind if one goes with the chopper - transformer - amplifier configuration (e.g. like the EM nV preamplifiers).