[SAM C] Analogue ground

[Simon]

Looking at the 32 pin SAMC device there is a common ground. Looking at the 48 pin device they start to name the ground pins near the analogue power pins as analogue ground.

I take it that there is no physical separation of ground and that it is just a case of the ground near the analogue supply is connected mainly to the analogue side of the chip as well as the rest.

So is it worth making an effort to separate the "two grounds"?

[T3sl4co1l]

I haven't had an application where a separate ground was needed at the MCU.

I absolutely do not recommend a beginner to cut ground planes!

I have had applications where ground cuts may be relevant, but those were using external ADCs, with design requirements in the 16-24 bit range -- far more accuracy than any garden variety MCU offers, anyway.  And being external, ground cuts at the MCU obviously aren't an issue there.

If you want to extract absolute maximum performance from your ADC, well, first I would recommend considering an external one -- even if you don't need more bits, onboard ADCs tend to be awful, plus this moves the analog side away from the noisy digital stuff to begin with.  Basically, echoing the above sentiment.

The second thing I would recommend: perform differential measurements, or use a calibrated reference or something.  You might use op-amps to translate input signals from a local ground plane (or fully differential source) to the local MCU ground.  Or you might bring the remote reference into the ADC as another signal, sample it, and subtract it from all the other signals (digital differential measurement).  There are many possible calibration options.  External VREF; ratiometric sensing; even dithering (including additive noise and filtering, and subtractive dithering).

I will note about ratios -- there's very little point in tracking units digitally.  I'm personally amused that e.g. 4.096V references exist (a typical complement to the very common 12-bit ADC).  Who cares what 1 LSB is, if it's some arbitrary ~1.0something mV or what?  It's just a ratio, 1/4096th of full scale!  Doesn't matter what the scale is!  You only need to know the scale when the number is printed (in which case multiply it by a calibration factor, which may be variable anyway!), or sent to something on a different gain scale (in which case you still don't need a true calibration factor, only the gain ratio between the two systems; but it may happen that both are calibrated, so the first case will suffice then).

Tim

[Simon]

You mean you have split grounds where there is separate analogue circuitry but you would not justify splitting the ground for an MCU even if it has a 24 bit converter. I don't plan to use 24 bits of resolution for these applications.

[T3sl4co1l]

"May be", not "is".  As it happens, the latest case, a design I did last year, was made with 100% solid ground pour, but I offered the customer the option of fabbing it with slots.  (We didn't do both, so I don't know if there would've been any benefit in this case.)  In any case, it was routed as well as possible following local ground-loop conventions.  (The result was, readings comparable to the datasheet noise floor, i.e. about a hundred counts out of the 24-bit range.  This at least implies we weren't going to do much better, anyway.)

I think there are MCUs with >=24b converters, but they're special purpose, e.g. highly integrated battery (charge monitor) or power line meter (including revenue grade) applications.  As such, I would also make special consideration for their use.  I won't go into anything generic here.

Under 16 bits, and < MSps, I find it hard to think of any possible justification for split planes.  Which is the range where most MCU ADCs lie.

Tim

[Simon]

well anything analogue I do is generally a slow changing signal that can be sampled multiple times and averaged. I am just doing a basic multipurpose system so while I want to future proof it i don't want to make life difficult (mission creep).

[ataradov]

Don't bother. It is useful to know what ground pins are what, but in practice it makes no difference, just connect them all to the same ground plane.

[uer166]

Under 16 bits, and < MSps.

What about beyond that? Say 24bit ~100ksps dedicated ADC, or a fast-ish 5msps 12 bit ADC..

[T3sl4co1l]

The first one sure, the second one you're still a ways up from the noise floor.  A 50 ohm source in <50kHz BW (100kSps) has 0.1uV RMS noise, or ~2 LSBs out of 24 bits at 1V reference.  At 2.5MHz, the noise rises to only 0.7uV RMS, whereas 1 LSB out of 12 bits at 1V reference is a whopping 250uV.

ADCs in the 50MSps range and >= 12 bits tend to run into a noticeable noise floor.

Worth noting that the sampling aperture matters; the analog bandwidth of the ADC itself.  Even if the source is carefully filtered, if the ADC is presented with a resistance at all frequencies, it's actually sampling at its analog bandwidth, not its intended bandwidth.  This is a good reason why some ADC coupling networks recommend an RC filter / terminator at the ADC input: it gives a low impedance, and therefore low V/rtHz, for frequencies above the intended bandwidth.

Put another way, an ADC with 500MHz analog bandwidth (so, well suited to equivalent time sampling and SDR applications), is always reading 500MHz of bandwidth from a resistive source.  Even if it's sampling at only 10MSps or whatever.

Consider the statistics: there are effectively more trials (~1 every ns) for the resistance to generate a new noise value v[n] = e_n * rnd(), and the ADC is simply sampling one of them every so often.  Doesn't matter how often you sample, it still has the expected amplitude e_n.

Another way to think about it: it is doable in principle to measure the RMS value of any signal, with exactly one sample -- because, what is the expected value (RMS) of that sample?  Well, it's the RMS, of course.  The error bar just happens to be atrocious (1 point does not, a representative sample, make!).  More practically speaking, as long as your sampling is uncorrelated to the signal, and the sampling bandwidth includes the signal bandwidth, then you can compute RMS from those samples, with the the usual statistics (i.e. an error on the order of 1/sqrt(N)).


In any case -- the magnitude of these LSBs, and noises, gives you the template you need to evaluate the performance of a design.  Presumably, you should ensure coupling from digital signals (a few volts) to the ADC is in the < -70dB range (for 12b).  That includes ground bounce and other EMC relationships.  PSRR needs to be similar, and if it cannot be obtained from the opamps/ADCs themselves, then filtering is needed to ensure supply noise is similarly attenuated (whether the reference noise from a linear reg, or switching).  Then PDN analysis applies, and optimization can be straightforward.

Tim