32F4xx + LAN8742 PHY + RJ45 - best location for PHY?

[peter-h]

I need to have the integrated-mag RJ45 about 15cm (track length) from the CPU.

The PHY can be near the CPU or near the RJ45.

Which is better?

I think near the CPU is better because of that 50MHz clock PHY -> CPU which will radiate like hell, even when tweaked with a 22R etc.

[nctnico]

Yes, place the PHY close to the CPU. The ethernet lines (analog signals) are much less of a problem. Make sure to allow inserting series resistors or ferrite beads in the signals going to the RJ45. In most cases 5 Ohm or a 10 Ohm ferrite bead is needed with cheap phys to pass EMC. Also make sure to have power planes and decoupling for the pins supplying the output driver of the phy. Those Microchip phys are horrible from an EMC perspective. What you save on the phy you need to spend on failing certification testing and extra filter parts. Been there, done that. In my designs I'm using the industrial, low-emi phys from TI.

[Doctorandus_P]

Or use an STM32 with built in PHY? I think STM32F407 is one of those, but ST has thousands of chips so use a search engine for your peripheral mix.


https://mongoose.ws/articles/stm32-ethernet-explained/

https://www.st.com/resource/en/user_manual/um1713-developing-applications-on-stm32cube-with-lwip-tcpip-stack-stmicroelectronics.pdf

Ar as I know, LWIP is a pretty reasonable TCP/IP stack. It's open source, has been in use for over 20 years and is still under active maintenance.
https://en.wikipedia.org/wiki/LwIP


Edit: Oopsie, I got a bit confused between MAC and PHY.

[peter-h]

place the PHY close to the CPU. The ethernet lines (analog signals) are much less of a problem

I did some digging and TI recommend the opposite; reasons given: longer traces on the high speed MDI lines will act like antennas and radiate — i.e. extending MDI is the worse choice, which by implication means keeping the PHY near the connector (short MDI) and extending the RMII bus back to the MAC is the recommended direction.

But I can well see 100mbps ETH radiates less than a 50MHz "square wave" clock.

I put this to Claude:

The most directly relevant data point is a real engineer comparing both parts in real designs: a TI forum poster ran the DP83848 in one design and the LAN8742A in another, and both failed EMC at the same harmonic frequencies (200, 250, 550MHz). Crucially, they identified the actual causes as layout issues specific to their board — PHY-to-MCU distance, MDIO/MDC not properly impedance-matched as a differential pair, and magnetics sitting without ground/power plane underneath — not anything inherent to either chip. TI's own EMI app note (SNLA107) frames radiated emissions as fundamentally a common-mode-energy problem driven by signal balance, termination, and layout partitioning — the same conclusion.

In my designs I'm using the industrial, low-emi phys from TI.

Which ones are you using, and how much work was it to change the code? There is an awful lot of code interfacing to a LAN8742 for example.

[langwadt]

Or use an STM32 with built in PHY?

I'm quite sure no such thing exist

[dietert1]

As far as i remember, signals between the phy and magnetics/RJ45 are differential. If designed correctly, radiation from those connections can be small. So the phy should be next to the MCU. One can make a prototype and try to adjust residual timing differences with delay traces similar to what we see on dimm modules in order to improve compensation.

Regards, Dieter

PS: I remember a fiber ethernet make that i showed here: https://www.eevblog.com/forum/microcontrollers/stm32f7-h7-lwip-webserver-problem/msg5542753/#msg5542753. It involved a different phy supporting the fiber mode. Adapting the STM supplied driver file was easy, maybe one day or so.

[nctnico]

As far as i remember, signals between the phy and magnetics/RJ45 are differential. If designed correctly, radiation from those connections can be small.

Indeed. The lines between the phy and magnetics are differential so their fields cancel. But in the end dealing with differential lines needs proper routing techniques. In my most recent 10/100 design I used a DP83825I and I have put 4.7 Ohm resistors in series with the lines going to the magnetics. The energy content of ethernet signals drops sharply above 125MHz. But the cheaper phys can be prone to outputting common mode harmonics onto the ethernet lines which then travel through the transformer.

[peter-h]

I have put 4.7 Ohm resistors in series with the lines going to the magnetics

How lon were those traces?

In my design I will have freedom on the size of the relevant tracks, including putting them between planes (6 layer board).

[nctnico]

I have put 4.7 Ohm resistors in series with the lines going to the magnetics

How lon were those traces?

In my design I will have freedom on the size of the relevant tracks, including putting them between planes (6 layer board).

7 cm or so.

[peter-h]

Interesting those 7cm were critical and then you can run 50m of the ETH cable as twisted pair, supposedly in compliance with CE / EN xxxxx

Also interesting that a Vcm generated by the PHY made it through the magnetics, which make the other side floating.

[fchk]

I need to have the integrated-mag RJ45 about 15cm (track length) from the CPU.

I suggest putting the magjack and the Phy close to the MCU and use a 20cm shielded CAT5 cable and a keystone connector for the remaining way. The cable is shielded and the pairs are properly twisted and as symmetrical as it gets.

fchk

[peter-h]

That would be messy to do.

There is a company called Datapro that makes panel mounting RJ45 jacks with a lead attached, about 1ft, so these could be cut down to length etc. But still messy. That cable has to be supported, against vibration etc.

In one project I have 1cm PHY-CPU and then 1cm PHY-RJ45. So that should be good

In this next one, the CPU and the RJ45 are about 10-15cm (track length) apart.

What this comes down to, I think, is that for either the RMII tracks or the MDI (?) tracks I have complete freedom to create the correct transmission line properties. So surely it must be possible, one way or the other. Most of the distance will be on a single PCB, 1.6mm, and this can be 6-layer, so I can use an impedance calculator to do it correctly. I even looked at Rogers material but apparently this is wasted for these frequencies.

FWIW, this whole thing will be in a metal case, all six sides conductively anodised and electrically connected. Obviously this will almost eliminate radiated EMI but not conducted. But also I do not want to radiate excessively internally, which is why I can go to 6 layers for the PCB and run these tracks between layers.

What impedance should I aim for for the PHY-RJ45 tracks? Presumably the best one is the differential pair to be adjacent tracks and between layers, but none of the online impedance calculators make it clear how to achieve this.

[nctnico]

Interesting those 7cm were critical and then you can run 50m of the ETH cable as twisted pair, supposedly in compliance with CE / EN xxxxx

Also interesting that a Vcm generated by the PHY made it through the magnetics, which make the other side floating.

Yes. But keep in mind the magnetics where at the edge of the board. Not near the phy. And yes, this product passed CE and FCC testing with the lowest limits for consumer / industrial products.

For the PCB design the single ended impedance should be 50 Ohm and the differential impedance 100 Ohm. What can make 10/100 Mbit challenging are unused pairs in the ethernet cable. If you can, use the Bob Smith termination to terminate unused pairs. The typical 10/100 Mbit magjacks have this internally.

[SiliconWizard]

For RMII (10/100 Mb Ethernet PHYs), placing the PHY closer to the magjack can be defended, although 15 cm is starting to be a bit on the long side. I have seen numerous app notes indeed suggesting to place the PHY closer to the magnetics, but they rarely deal with such long distances between SoC/MCU and PHY.

If it were RGMII (1 Gb PHYs), I would definitely consider 15 cm to be too long.

I think it's reasonable to place the PHY closer to the MCU and carefully route the MDI lines, which are differential pairs, to the magnetics. You'll have to use controlled impedance to maximize your odds of passing EMC.

[peter-h]

Right. This is what I arrived at



The stack-up is JLCPCB's, with very unequal dielectric above and below the signal tracks, and actually slightly different Er too.

[nctnico]

I'd investigate whether you can get to a diff pair with less space in between. Putting the traces on the top or bottom layer might be a better option. The rule of thumb is to keep diff pairs apart 5 times the spacing for the pair. That is going to take quite a bit of space.

[peter-h]

The PCB will be 6 layer so I could create five differential pairs, all between layers, and all hidden. Just no components on the outside of the PCB in that area, about 0.2" wide. That's not too bad. Each will be slightly different due to the different layer thicknesses

Actually there are only 2 differential pairs on a 10/100 RJ45

[harerod]

- is the connector with integrated magnetics a given?
- could placing PHY and magnetics next to the MCU and routing the actual ETH signal to a connector be an option?

[peter-h]

Practically yes because I have them in another product.
It could be, but what would it gain to have a plain RJ45 and the old style magnetics?

[nctnico]

- is the connector with integrated magnetics a given?
- could placing PHY and magnetics next to the MCU and routing the actual ETH signal to a connector be an option?

That is not a good idea. You'll bring all the nasty stuff that can be on the cable onto your circuit board. A typicall LAN transformer includes some common mode filtering so that is your first line of defense keeping external noise out of your board.

[SiliconWizard]

Yeah. Maybe he was thinking more in terms of signal integrity rather than EMI, but overall that would probably not be a very good idea.

[amyk]

https://www.servethehome.com/wp-content/uploads/2025/09/GiGaPlus-GP-S252402-24-Port-2.5G-Ethernet-Switch-with-2x-10G-SFP-Inside-1.jpg and that's running at least 25x faster than your design

[peter-h]

Right, but that's designed for absolute minimum cost. They are using RJ45s which are 10-20p each. Integrated-mag RJ45s are ~£1, for Hanrun or Link-PP; half that for counterfeit ones (which on my tests seem to work just the same).

And they have short connections.

[harerod]

Yeah. Maybe he was thinking more in terms of signal integrity rather than EMI, but overall that would probably not be a very good idea.

This is one of those questions where the whole setup must be known to find a satisfactory trade-off. Otherwise you start playing whack-a-mole with the different design constraints.

[peter-h]

What kind of line driving resistors should be placed into the signals going from the LAN8742 to the integrated-magnetics RJ45?

The signals are "analogue" so should not be square wave at this point.

I would think probably nothing should go in there. But is there really no harmonic content?