I don't understand this discussion... The idea is push 6Gbps of data into the memory and then what? Let's say you can achieve that speed, but you have absolute zero time then to read and process that data. The bus will always be busy writing.
since you asked, lets open the worm can a little bit more. as i said earlier, during capture, the circuit will get input data to adc->fpga->ram at 6GSps until 50-100MB of RAM is filled up. after that, its called blind time, no capture but processing the data RAM->processor->display. how long is this blind time? its unspecified and mainly will depends on how fast post-processing is made. but i have the feeling that it is 99.999% certain that post processing will take alot slower to complete than capture rate, so any funny idea such as double buffering will be inapplicable here, except if i have to tolerate super expensive solution such as massive parallel processing involving super expensive fpga or massive amount of them marched/arranged on the pcb like brain cells. there are few possibilities during this "blind time":
a) another mcu or fpga is connected to the same bus where writing to the RAM from FPGA is made during capture, but this time fetching the data out of RAM from the same bus for FFT processing (at slower speed if cannot be fast). or if write and read can be done concurrently for the RAM from different bus, then so be it. i'm not sure if this even possible, i've never done this.
b) the same fpga which wrote to the RAM earlier will fetch back the RAM content for FFT processing, or maybe process the captured data concurrently (while capture in progress) but this will depend on algorithm used.
c) same as (a) except reading bus is from another pin of the 1st (capture) fpga. ie for reading RAM, mcu has to command the capture FPGA to read the RAM and send the content to the another output bus to mcu or another fpga.
i should sketch something
but i'm in the office right now, MechCAD is a bit difficult from here here we go (see attached). anyway this is what i can think of from spherical dead cow point of view. as for RAM, what i prefer is, it should not have the "refresh cycle" or internal housekeeping job that blocked writing to RAM. if capture fpga has to wait for the RAM to do something then its not good (unless the condition can outrun the capture rate). i prefer a RAM that we simply set the address either to serial or parallel pin, and incremented by shift register or something, if RAM can automatically increment the address internally without fpga doing anything, then this is the ideal RAM i'm looking for. another thing is how to fetch data from ram, is from the same bus? or is ram have another pin for output, this i need to study later and will impact design decision, this is another deeper into the worm can or the spherical dead cow gray matter stuffs.
feel free to share thoughts, my intention for this thread is already answered, ie the question of "whether a fpga can do 6GSps". My best regards to you all.