A couple questions about Milk-V Duo boards

• A couple questions about Milk-V Duo boards
  Posted by SiliconWizard on 24 Apr, 2024 07:52
• Interested in evaluating the CPU they use. I haven't ordered boards yet.
  
  Does anyone know:
  - How the C906 core compares to say a Cortex-M7 (namely the main C906 core @1GHz vs a iMXRT10xx @600MHz, for instance)?
  - The approximate current draw under typical load, and any "sleep" mode it may have?
  - Whether it's possible (probably) but, most of all, documented, to program the main core baremetal (no Linux)? If so, is there any documentation out there? (I've seen the typical setup was Linux on the main core and some RTOS on the second core, I'd like to use both cores baremetal).
  
  Thanks!
• #1 Reply
  Posted by brucehoult on 24 Apr, 2024 08:16
• On my primes benchmark:
  
  

  Code: [Select]

  //    27.196 sec Teensy 4.0 Cortex M7 @ 960 MHz        228 bytes  26.1 billion clocks
//    27.480 sec HiFive Unleashed RISCV U54 @ 1.45 GHz 228 bytes  39.8 billion clocks
//    30.420 sec Pi3 Cortex A53 @ 1.2 GHz T32          204 bytes  36.5 billion clocks
//    36.652 sec Allwinner D1 C906 RV64 @ 1.008 GHz    224 bytes  36.9 billion clocks
//    39.840 sec HiFive Unl RISCV U54 @ 1.0 GHz        228 bytes  39.8 billion clocks
//    43.516 sec Teensy 4.0 Cortex M7 @ 600 MHz        228 bytes  26.1 billion clocks
//    47.910 sec Pi2 Cortex A7 @ 900 MHz T32           204 bytes  42.1 billion clocks
//    48.206 sec Zynq-7010 Cortex A9 @ 650MHz          248 bytes  31.3 billion clocks

  The D1 is not the same chip as the Duo but it's the same core at the same speed, and this benchmark runs entirely in cache.
  
  > The approximate current draw under typical load, and any "sleep" mode it may have?
  
  See:
  
  
  
  In the comments:
  
  Without SD card: 15mA
  
  Booting: 80-114mA, average about 90.
  
  Idle after boot: 62mA
  
  > Whether it's possible (probably) but, most of all, documented, to program the main core baremetal (no Linux)?
  
  Sure. The UBoot is, after all, open source, so you can either use that to launch your own code (replacing OpenSBI) or else simply hack on the UBoot SPL. The biggest task will be initing the DDR2 RAM, but the code is there.
  
  
• #2 Reply
  Posted by SiliconWizard on 24 Apr, 2024 22:27
• Thanks! So, in terms of pure performance, at least from your benchmark, the C906 looks way behind a Cortex-M7 at the same clock freq, but not too far between a M7 @600MHz and C906@1GHz.
  
  In terms of power draw, the "missing" info is whether it has any kind of sleep mode, which you can go to and resume from, either when running Linux, or baremetal.
  62mA on "idle" is not bad for a CPU @1GHz, but the ability to put it in some standby mode drawing much less, and from which it could get out of within maybe less than 1s, would be nice. I haven't found the info so far and may have to order boards and figure it out myself.
  
• #3 Reply
  Posted by brucehoult on 25 Apr, 2024 01:35
• Quote from: SiliconWizard on 24 Apr, 2024 22:27

  Thanks! So, in terms of pure performance, at least from your benchmark, the C906 looks way behind a Cortex-M7 at the same clock freq
  

  
  Sure. The M7 is a pretty good dual-issue uarch -- better than A7, A9, A53, maybe close to A55. And running from SRAM not DRAM helps too. The C906 is purely single-issue, in order.
  
  Note that the Duo has massively more RAM with 64 MB (and 256 MB and 512 MB models just becoming available for only a few dollars more)
  
• #4 Reply
  Posted by SiliconWizard on 25 Apr, 2024 01:41
• Yep. The amount of RAM can be pretty interesting. Using a Cortex-M7, you rarely have access to anything else than PSRAM if you want more than the internal RAM, which is slow and limited to 8MB/chip (at least for the QSPI ones), or maybe SDRAM for some MCUs?
  
  The Duo's with 256MB and over are slightly different beasts as I've seen, they include an ARM core on top of the 2 RISC-V cores. I haven't figured out yet how all 3 can work together.
• #5 Reply
  Posted by brucehoult on 25 Apr, 2024 04:18
• I think you have to choose one or the other at boot time, but I don't know.
  
  Also see:
  
  https://github.com/orangecms/sg_boot "loader for CVItek/Sophgo SoCs (CV1800B, SG200x)"
  
  He said today initial stuff is working and asked for collaborators.
  
  https://t.me/riscv/1/20904
  
  https://t.me/riscv/1/20913
  
• #6 Reply
  Posted by brucehoult on 26 Apr, 2024 02:40
• More progress today:
  
  "Daniel aka CyReVolt 🐢: Transferring code to the CVITek 1800B worked with my tool. There was no output on the UART though. I'll see if the SRAM address is different, which isn't described in the manual. UART0 seems to have the same base address per the manual."
  
  "plat/cv180x/include/platform_def.h
  296:    #define VC_RAM_BASE 0x3BC00000 // Shadow_vc_mem"
  
  "Daniel aka CyReVolt 🐢: aha aha - 0x3BC00000 - neither "VC RAM" nor that address is mentioned in the manual"
  
  "Daniel aka CyReVolt 🐢: THAT WORKS! VROOM VROOM! 🥳"
  
  "I have now successfully run my own code on
  - Duo (CV1800B)
  - Duo 256M (SG2002)
  - Duo S (SG2000)
  
  The CV1800B has its SRAM at a different base address.
  UART0 is mapped to the same address for all three."
  
  His "own code" is written in Rust. Blergh for some people, ++ for others :-)
  
  A note on chip names and companies ... Sophgo bought Cvitech a year or two ago, so CV1800B and SG200* share lineage.  Also, a well informed Chinese person on Telegram said a couple of days ago that Sophgo and Radxa are parts of the same company, or fall under the same umbrella company (Bitmain?). I just found this repo, which lends support to this: https://github.com/radxa/bm-bootloader-arm64