Good morning,
I am in the design phase of a SMPS GaN based that will operate at around 1MHz with many four-switch Buck-Boost (FSBB). Most of the MCUs for this kind of applications only have 8 pairs of high res. PWM (around 150ps) but I need more. Having an MCU with more high res. outputs increases its price significantly.
I have thought of using the “Configurable Logic Cell (CLC)” that many of these microcontrollers have for generating complementary outputs and only using one pair for every full-bridge thanks to some logic.
I found an Application Note from Microchip Technologies that talks about this possibility in Fig. 11.
https://ww1.microchip.com/downloads/en/AppNotes/00002133a.pdf
dsPIC33CK include this block:
https://ww1.microchip.com/downloads/aemDocuments/documents/MCU16/ProductDocuments/DataSheets/dsPIC33CK1024MP710-Family-Data-Sheet-DS70005496.pdfWhat do you think about this possibility for high frequency application? Feasable?. I am afraid about possible delays this block could produce but cannot see why it would not work.
Best regards,
Miguel.
Hi,
check the device datasheet. You can't use just any peripheral signal with CLC (see the CLCxSEL register!)
Altough, it might be possible to take one of the HSPWM with PPS output and route to CLCINx via virtual connections, but i don't have a device at hand to test if it works. Even if it worked, only PWM4 can be routed through PPS in the dsPIC33CK2556MP508 family.
I couldn't find timing specifications for the CLC, so additional delays are not characterized.
If you can live with some channel at lower frequency PWM, remember that you have 8 pair of HSPWM + 1 MCCP (which can do full bridge/deadtime) + 8 SCCP (which require CLC trickery to achieve full bridge/deadtime)