Multicore is a form of multiprocessing. A multicore processor has multiple cores(!) in the same processor (same die, or same module). This means they usually share L3 and L2 cache, and are more tightly coupled than processors in different sockets.
I am playing with an SMP dual cpu module, 2xR12K processors (MIPS4, 64bit, they are not cores, they are physical chips, two R12K chips), and it uses a completely different method to "pass" commands between CPU0 and CPU1, it's different from e500 quadri-core.
I do not know which kind of atomic instructions are used, e.g. 68000 uses TaS, Test and Set, as read-modify cpu-cycle, I do not know about the cache coherency algorithm. Snoop protocol ? just heard in my computer science course, 4 years ago, what else is used?
and what about coherency algorithms ? I have found the following list in my R12K handbook, while linux implements and uses the 5th, cacheable, coherent, write-back, exclusive on write, sharable (even if … on my board it's not working at all
)
/*
* MIPS3_TLB_ATTR (CCA) values - coherency algorithm:
* 0: cacheable, noncoherent, write-through, no write allocate
* 1: cacheable, noncoherent, write-through, write allocate
* 2: uncached
* 3: cacheable, noncoherent, write-back (noncoherent)
* 4: cacheable, coherent, write-back, exclusive (exclusive)
* 5: cacheable, coherent, write-back, exclusive on write (sharable)
* 6: cacheable, coherent, write-back, update on write (update)
* 7: uncached, accelerated (gather STORE operations)
*/