ARM Cortex-M implementations

[Unixon]

Every time I see a new ARM MCU from a previously unknown manufacturer I have exactly the same question on my mind: how compatible is this one with other ARM MCUs with the same core?
What parts could possibly change and what parts could not? Would I be able to make a firmware for that new MCU and program it or not?
Well, the ISA is definitely not changing, OK, but ABI can change and I saw Chinese clones doing exactly that - shuffling bits around.
What about memory map? How badly could it be mixed up? Peripherals - definitely could be different and differently mapped.
What part about ARM (or any other architecture) could we trust at all to stay exactly the same across different implementations?

[langwadt]

Every time I see a new ARM MCU from a previously unknown manufacturer I have exactly the same question on my mind: how compatible is this one with other ARM MCUs with the same core?
What parts could possibly change and what parts could not? Would I be able to make a firmware for that new MCU and program it or not?
Well, the ISA is definitely not changing, OK, but ABI can change and I saw Chinese clones doing exactly that - shuffling bits around.
What about memory map? How badly could it be mixed up? Peripherals - definitely could be different and differently mapped.
What part about ARM (or any other architecture) could we trust at all to stay exactly the same across different implementations?

instructionset, nvic, systick, debug core, should be the same. the rest vendor specific

[gf]

The following documents apply universally to each silicon vendor:

Arm Architecture Reference Manual for the specific architecture version (e.g., ARMv7-M)
Arm Technical Reference Manual for the specific processor (e.g., Cortex-M4)

The Arm Architecture Reference Manual outlines all possible capabilities for the ARMv7-M generation, but the Cortex-M4 TRM dictates the physical implementation rules, distinguishing between mandatory requirements and configurable options. Because optional features (such as the FPU or MPU) are implemented at the vendor's discretion, you can strictly rely only on the core mandatory features guaranteed by the TRM if you want to ensure absolute software portability across all Cortex-M4 vendors. The vendor's reference manual (or datasheet) is supposed to specify which of these options are actually implemented.

While the HAL provides a uniform software interface, it cannot instantiate absent hardware; you still cannot access optional features like the MPU if the vendor chose to omit them.

[westfw]

There are "optional" features for each core.  It's nice if the vendor's datasheet provides and explicit callout in the datasheet of what they've actually implemented (SAMD21 From Atmel/Microchip example):

but ABI can change and I saw Chinese clones doing exactly that - shuffling bits around.

I'm not sure what you mean by that.  The "ABI" is normally a software thing, not dependent on the "core."

[Unixon]

I'm not sure what you mean by that.  The "ABI" is normally a software thing, not dependent on the "core."

I believe someone mentioned it on the forum recently that they have encountered a Chinese ARM MCU clone fully implemented architecturally but binary incompatible because of swapped bit fields in instruction codes and other obfuscation. However, those Chinese guys were not claiming that still being an ARM to avoid license payments to ARM Holdings.

[Unixon]

Considering features that are either mandatory or optional, what is exactly defined about them? Control register layout? Memory mapping of control registers?
Haven't read RMs yet...

[NorthGuy]

Considering features that are either mandatory or optional, what is exactly defined about them? Control register layout? Memory mapping of control registers?
Haven't read RMs yet...

There are registers which let you see if a particular optional feature is included, cannot tell about all features though. Usually you don't need to worry about these except for major things such as FPU.

Some of registers come with the core. Major memory areas are determined by the core, but not details. It's all in RM.