The two masters either try to talk to the same slave and want to tell the same (e.g. write the same data into the same address, or read from the same address) - and in that case the two SDA sequences are identical and there's no conflict, no one of the masters need to take over - or there is at least one bit difference.
In the latter case, one of the masters (say M1) outputs onto SDA 0 and the other (say M2) 1. Due to wire-OR and open collectors, SDA is in state 0. Each master reads back after each bit the state of SDA, and as M2 intended to output 1 but the SDA is at 0, this master simply gaves up, and the rest of the stream is under control of the other master i.e. M1.
JW