Author Topic: CPU crystal "pull" range and how critical are the caps, for e.g. USB FS  (Read 13742 times)

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Offline peter-hTopic starter

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I have a 32F417 design, and after a couple of years of building little batches, qualifying various components (e.g. RJ45 integrated jacks from Hanrun and fake-Hanrun, various xtals, etc) while developing the software, I am now building an initial "pre production" batch of 100.

Over the years I've evaluated various crystals. There are two: 25MHz and 32768Hz - as usual. The 25MHz one is scaled up to 50MHz for ETH and to 48MHz for USB FS.

The problem is that these crystals are hard to buy the same one twice :) For example CX3225GB25000P0HPQCC comes in about a dozen endings after the 25000. Some of these are documented in the data sheet but not all. For example this one
https://www.mouser.co.uk/ProductDetail/KYOCERA-AVX/CX3225GB25000P0HPQZ1?qs=WtbxmXO%2FfWTKVKFSKFjSnA%3D%3D
is no longer available, but this one is
https://www.mouser.co.uk/ProductDetail/581-CX3225GB25PHPQCC
There are also mistakes in the disti's spec summary, and they vary between Mouser and Digikey.
This one is in stock at Mouser
https://www.mouser.co.uk/c/?q=FA-238%2025.0000MB-G0
but I am unable to find the spec for it anywhere; certainly the data sheet doesn't appear to mention the "G0".

Some are "18pF" and some are "20pF" which seems ridiculously close.

For many years I used AEL Crystals, which basically sell no-name chinese crystals which are about 1/4 the cost of the Kyocera or Epson ones above, but now AEL want a £1000 min order value, which I can do but don't want to do it right now. Luckily I did qualify crystals from them in years past, before they did this MOQ thing. I don't know who actually pays 45p for a crystal in production??? Two other outfits, IQD and Euroquartz, only do pricey stuff now.

So we get to the crux of the question. One is working only with guesses for the CPU pin capacitance and the PCB track capacitance. Some estimates for these are 5pF and some are 10pF, per pin. I think 5pF is probably nearer, with a compact oscillator layout, with a ground plane under it all. I have read up it for hours and all I see is websites showing a ton of oscillator formulae and nothing actually useful. How much is the oscillator frequency going to be pulled out if you get the capacitance seen by the xtal off by say 5 or 10pF? I have a feeling it will be only a few ppm and nowhere near enough to affect ETH or USB FS.

I have never actually measured the frequency; I don't have a frequency counter and anyway it would need to be a good one, and sensitive so no connection is needed. I have a Marconi 2024 sig gen and an Anritsu spectrum analyser which could work off a no-contact probe, but the oscillators in these are no better than 10-20ppm anyway.

I've also seen ETH and USB FS designs work with crystal resonators - about 0.5% i.e. 5000ppm. And this is not the USB which syncs off the Host, either...

For final amusement, the STM eval board uses a 1M resistor across the xtal, which is normal except that you don't need it because the 32F417 has an internal 200k one. Whoops :) I don't use a resistor...

It is pretty obvious that this whole business works on the blind leading the blind and the answer probably is "it doesn't matter" :)
« Last Edit: February 20, 2024, 06:04:20 pm by peter-h »
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Offline T3sl4co1l

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Re: CPU crystal "pull" range and how critical are the caps, for e.g. USB FS
« Reply #1 on: February 20, 2024, 07:22:03 pm »
The ST appnote is one of the more convincing / well written ones:
https://www.st.com/resource/en/application_note/an2867-oscillator-design-guide-for-stm8afals-stm32-mcus-and-mpus-stmicroelectronics.pdf
maybe ironically -- but perhaps because of -- their somewhat notoriously? weak oscillators.  That is, they tend to use lower drive current, or less transconductance, than most, necessitating a higher ESR (lower CL) crystal than average.

There indeed exists a methodical design and testing procedure for crystal oscillators.  The main problem is, whether required supporting information is available (e.g. gm of oscillator, at frequency, and at drive strength/mode(s); Cstray, Rfb, etc.), and whether min/max/median parts are available to actually test, plus env chamber to run at temp extremes, and supply voltage extremes; and, most of all, whether the budget and time is there to actually perform such testing, versus whether it's worthwhile at all.

Conversely, you can buy and measure random crystals: Fo, Cs, CL, ESR, ppm/°C, pulling, etc.  But this is a bit of work, and moderately specialized hardware is required (I suppose 32kHz crystals you could do with a sound card, but mostly you'd want a VNA, of adequate spectral purity to resolve such narrow resonance), and if you're actually going to sort random parts, there's maybe no guarantee they'll be supplied consistently either, and now you've developed a receiving parts test program at whatever expense it is.

And as you can see, it can take specialized hardware.  An AC current probe to resolve µA into a crystal, is not exactly trivial.  Most people don't have one of those handy, and it's going to be special order.  A regular 10x voltage probe is insufficient as well: Cload is significant even for MHz crystals, and both Rload and Cload is too much for most watch crystals (100s kohms).  A FET probe is probably best; easy to make, at least, but also easy to fry, and if one doesn't want to make it, it's still another instrument to buy.

The principle of least surprise tends to apply, then, with no one bothering to test, and assuming the most common parts and most commonly repeated circuits are valid.  And they do usually work, but no one knows what the production yield is, whether they conk out at low or high temperature, whether complaints / service calls / warranties can be traced to it or not, ..., and yes, it can be "blind leading the blind".  Or perhaps, "blissful led by the ignorant", to merge with another phrase.

Regarding USB and Ethernet, at least, they're quite tolerant as far as I know -- but also, you'd have to know what the interfaces actually do, to know what clock tolerance is really acceptable; to know how they degrade if at all along the margins of that range; those sorts of things.

---

As for pulling -- note the C-crystal-C 'pi' structure acts to invert the parallel resonance to a series one, roughly speaking; C is inversely proportional to Zo of the filter.  So you have an impedance there, and that impedance must be near the oscillator's required load impedance (or 1/gm or whatever, plus margin to ensure oscillation of course).  You can vary Cload to vary Fo, but you vary Zo as well.  You can also put C in series with the crystal, which reduces the crystal's effect (in the limiting case, there's lim-->0 capacitance in series, and all C in shunt -- no crystal in circuit at all!), i.e. the depth of the resonance, but keeps the impedance close to nominal while allowing you to reduce Cload.  In total, you have strategies to pull it a little bit, up or down -- as for depth of pulling, it's usually some 100s Hz, maybe a couple kHz at most -- and if you have poor initial tolerance but acceptable stability, this might be a strategy to make use of it, assuming of course the resulting range is outside what's required for the hardware driven by it.  But then you're also adding a calibration (trimming) step, maybe with a special probe to read the crystal (if a direct logic-level clock isn't available; usually Ethernet does have this, USB doesn't?), and the added test time starts to look like qualification testing, and...

As for that last part, hardware tolerance?  If it's not in the datasheet -- or it is, but you want to know more -- you'll have to ask the manufacturer, of course. :)

Tim
« Last Edit: February 20, 2024, 07:30:12 pm by T3sl4co1l »
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Offline SiliconWizard

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Re: CPU crystal "pull" range and how critical are the caps, for e.g. USB FS
« Reply #2 on: February 20, 2024, 08:06:36 pm »
USB FS is rather tolerant, which is why it can be handled on some MCUs with their internal RC oscillator and about +/-1% frequency accuracy. (Even higher error is probably still ok.)
So a small change in the value of the load capacitors on a crystal will not make any difference. You probably have already figured that given the typical tolerance on usual ceramic caps, 2pF over 18pF is about 10%. Which is the typical tolerance for cheap ceramic caps, even C0G. For better than +/-10%, they get more expensive very quickly. (Like at least 10x the price to get from +/-10% to +/-1%.) I don't think anyone ever bothered to use +/-1% C0G load caps for the crystal oscillators for MCUs outside of maybe very niche applications.

I'll have a look at the USB specs in more details to give you the exact tolerance that is specified for USB FS. But the above points should give you a clue about the relevance of bothering with the exact value of load caps.
 

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Re: CPU crystal "pull" range and how critical are the caps, for e.g. USB FS
« Reply #3 on: February 20, 2024, 11:16:49 pm »
Some estimates for these are 5pF and some are 10pF, per pin. I think 5pF is probably nearer, with a compact oscillator layout, with a ground plane under it all. I have read up it for hours and all I see is websites showing a ton of oscillator formulae and nothing actually useful. How much is the oscillator frequency going to be pulled out if you get the capacitance seen by the xtal off by say 5 or 10pF? I have a feeling it will be only a few ppm and nowhere near enough to affect ETH or USB FS.

FS-USB has tolerance of ±0.25% or 2,500ppm so xtals can easily meet that, even with 'lazy' load cap choices.
HS-USB has tolerance of ± 500ppm, so HS-USB designs should check to confirm their crystal is correctly loaded.


It's easy to find pulling data - see
https://ecsxtal.com/choosing-series-or-parallel-resonant-crystals-oscillator-design-and-load-capacitance/

that has a graph, which shows 10/20/40ppm/pF ballparks, increasing as the crystal load decreases. Roughly it is 2ppm/% Cap change. 10% C change is ~20ppm
Note that is nominal, the actual circuit ppm/pF varies with XTALI/XTALO pin, with XTALI having higher pulling than XTALO.

Some are "18pF" and some are "20pF" which seems ridiculously close.
yes, for most uses it will not matter.
However, if you buy an initial 10ppm spec xtal (which are becoming more common) that 10% change is a 20ppm movement.
The tricky part is knowing where inside that 10% your test crystal is, so you might measure a dozen boards and calibrate to that average, if you want good initial tolerance.


I have never actually measured the frequency; I don't have a frequency counter and anyway it would need to be a good one, and sensitive so no connection is needed. I have a Marconi 2024 sig gen and an Anritsu spectrum analyser which could work off a no-contact probe, but the oscillators in these are no better than 10-20ppm anyway.
It's a good idea to be able to check frequency, but you need to avoid loading the crystal when doing so, so usually some pin is set to toggle by a timer, and that is checked.

« Last Edit: February 20, 2024, 11:21:51 pm by PCB.Wiz »
 
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Re: CPU crystal "pull" range and how critical are the caps, for e.g. USB FS
« Reply #4 on: February 20, 2024, 11:34:02 pm »
is no longer available, but this one is
https://www.mouser.co.uk/ProductDetail/581-CX3225GB25PHPQCC

Looking at that it says

Description: Crystals 25000kHz 18pF With Thermistor

Do you really want one with a thermistor ? 
Usually those are used where you are making your own TCXO, and you need the xtal temp to correct things, and worry about single digit ppm ?
 

Offline SiliconWizard

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Re: CPU crystal "pull" range and how critical are the caps, for e.g. USB FS
« Reply #5 on: February 21, 2024, 12:45:26 am »
Yes, I also checked,+/-2500 ppm for USB FS - using some RC oscillator (as some MCUs offer) requires definite care, but being off by more than 2500 ppm with a crystal-based oscillator? You would literally need to do it on purpose. Just changing the load capacitors, the crystal would probably start oscillating at a harmonic, or stop oscillating altogether, before oscillating that far away from its fundamental frequency. Yes, even the +/-500 ppm of USB US is easy to meet with a crystal. Not so much with a RC oscillator though.
 
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Offline peter-hTopic starter

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Re: CPU crystal "pull" range and how critical are the caps, for e.g. USB FS
« Reply #6 on: February 21, 2024, 07:36:02 am »
Quote
Do you really want one with a thermistor ?

That seems to be nonsense since the data sheet does not show any connections for a thermistor. Just the two usual xtal pins. I think it is a mistake - unless the thermistor is in series with the xtal.

Both Mouser and Digikey point to a DS here
https://support.epson.biz/td/api/doc_check.php?dl=brief_FA-238&lang=en

Quote
Roughly it is 2ppm/% Cap change. 10% C change is ~20ppm
Note that is nominal, the actual circuit ppm/pF varies with XTALI/XTALO pin, with XTALI having higher pulling than XTALO.

That's super useful! And it shows that the effect is a lot bigger than I thought, even though nowhere near enough to affect USB.

Obviously I am more concerned about the oscillator not starting up, at temperature extremes.

I did read AN2867 during the design but struggled to apply the content in practice. Also look at e.g. this recommending 470k min



and this in the 32F417 DS :)



I am using 2 x 15pF caps, and 220R Rext.



Maybe the most practical way to qualify xtals is to do temperature tests with Rext values from zero to a "lot" and work out the margins.

As the appnote says, amusingly:



There is an obvious typo here; should be increase instead of decrease.


In my case, 15pF, the "capacitive reactance of CL2 is 420 ohms, but that is just the cap itself. The stray cap is on top. So if they reckon the divider formed by Rext and C2L2 should start at 2:1, I am in the right ballpark with 220R.
« Last Edit: February 21, 2024, 08:09:57 am by peter-h »
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Offline wek

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Re: CPU crystal "pull" range and how critical are the caps, for e.g. USB FS
« Reply #7 on: February 21, 2024, 09:18:20 am »
On STM32, to avoid the need for fine probes needed to sense on crystal oscillator itself without affecting it, one can output HSE onto MCO pin and measure there.

A poor man like myself with no good frequency counter would not be bothered to do even that, but would use a timer and a "known good" timing source like 1Hz output from GPS receiver on some channel of that timer, and a piece of software written to compare them.

Btw. the 0.25% requirement for USB_FS is for Device; for Host it is somewhat more stringent (but still not very critical for FS, am lazy to look up the number).

JW
« Last Edit: February 21, 2024, 09:22:20 am by wek »
 
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Offline peter-hTopic starter

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Re: CPU crystal "pull" range and how critical are the caps, for e.g. USB FS
« Reply #8 on: February 21, 2024, 09:42:32 am »
OK; I can also measure the 50MHz from the LAN8742...

EDIT: Mouser confirm their "thermistor" description for the CX3225GB25000P0HPQCC is wrong.

The G0 in FA-238 25.0000MB-G0 means 1000 on a reel.

It's all a mess.
« Last Edit: February 21, 2024, 01:12:00 pm by peter-h »
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Offline MT

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Re: CPU crystal "pull" range and how critical are the caps, for e.g. USB FS
« Reply #9 on: February 21, 2024, 01:43:16 pm »
The problem is that these crystals are hard to buy the same one twice :)
It is pretty obvious that this whole business works on the blind leading the blind and the answer probably is "it doesn't matter" :)
Thats because crystals are made in batches based on the max size of the final crystal growt.
https://youtu.be/lzHqhNoyx2o?t=178

Quartz crystal ageing is caused by many different factors. Different crystals age at different rates and is attributed to a number of factors
some in the manufacturing process and some by the way they are used.

Crystal surface change, crystal lattice contamination,thermal effects,wire fatigue,frictional wear,drive levels, encapsulating etc. 
The level of ageing can be minimised in a number of ways both in manufacture and in use:

By keeping the drive levels low the crystal ageing will be less.
The maximum rate of change of frequency occurs immediately after manufacture and decays thereafter its found that it is fastest within the first 45 days of operation.

« Last Edit: February 21, 2024, 02:37:07 pm by MT »
 

Offline T3sl4co1l

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Re: CPU crystal "pull" range and how critical are the caps, for e.g. USB FS
« Reply #10 on: February 21, 2024, 02:39:26 pm »
Maybe the most practical way to qualify xtals is to do temperature tests with Rext values from zero to a "lot" and work out the margins.

As the appnote says, amusingly:



There is an obvious typo here; should be increase instead of decrease.


In my case, 15pF, the "capacitive reactance of CL2 is 420 ohms, but that is just the cap itself. The stray cap is on top. So if they reckon the divider formed by Rext and C2L2 should start at 2:1, I am in the right ballpark with 220R.

Their discussion of Rext is peculiar, yeah.  s/decr/incr/ is a fairly simple typo, if a somewhat glaring one.

There are generally two types of oscillator in common use: current-limited or biased amplifier style, and schmitt trigger (logic output) style.  The latter as you can guess, has 3.3V or whatever full scale output, so would drive considerable power into the crystal, and maybe overvolt the input pin even if the crystal withstands that power.  A series limiting resistor, usually around 1k, sets the source/termination impedance for the filter, and sets drive power to a reasonable level.

The other kind, the amplifier can be modeled as an ideal gm amp, i.e. a current-source output, and the series resistance can be ignored.

Why ST suggests a resistor, then, is somewhat mysterious.

Now, it may be that the biased MOSFETs operate in or near the triode region, so that the incremental output resistance is not actually very high, and then Rext acts as a current divider with that impedance.  So too, the gm decreases sharply as the input voltage leaves the Q-point (i.e., gm(Vin) has a peak near quiescent, and dropping fairly quickly off to the sides).  This nonlinearity might be employed by itself to limit operating amplitude, without any tuning at all; and, I think this is a very common mechanism in use.

Perhaps ST doesn't have tight enough process control for that stabilizing mechanism; or that they intend the user to have some amount of freedom, say to tune it for even very small (low power limit) crystals?  That additional level of constraint wouldn't be something they can account for (or, not very practically given other limits like pin Cstray), but with Rext, perhaps scope can be extended just a bit farther.

It could also be a cascode style output stage, where Zo is high, and Io is roughly a rounded-step function of Vin (more precisely, something like a tanh function, but probably a bit lumper from the sum effect of multiple stages' nonlinearity).  This still exhibits amplitude limiting (average gm decreases with increasing amplitude), but Rext would have little impact on it.  It may finally also be, that the internal/pin Cstray is high enough to add a pole with Rext, therefore reducing crystal power and loop gain; it will also affect loop stability, detuning it a little (which I suppose is to say, sensitivity is higher than just the straight impedance divider ratio would suggest, hence the relatively small values suggested).

Tim
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Re: CPU crystal "pull" range and how critical are the caps, for e.g. USB FS
« Reply #11 on: February 21, 2024, 07:34:43 pm »
Why ST suggests a resistor, then, is somewhat mysterious.
Most MCU vendors do not bother, but as well as what you mention, the series R has other effects too.

Nexperia show some effects below, where they tabulate (with kMHz typo)  Rs for minimum Icc and Rs for lowest dF/dV  (74HCU04 data)

   ^^ Typo, they meant MHz, of course.

Most xtal amplifiers start as simple linear stages, but as the swings increase, they move to a more switched operation. The amplifier currents are far from sinewave.
Thus series Rs can also lower RFI.

Also, because oscillators also all need some buffer (often overlooked in analysis), some value of Rs can give minimum power consumption.

Rs can also improve startup times, which means it improves the overall phase.

If you are selling oscillators, or chasing lowest power, those details matter. Most MCU vendors just give the simplest circuit, so as not to spook the users.

« Last Edit: February 21, 2024, 07:37:05 pm by PCB.Wiz »
 

Offline T3sl4co1l

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Re: CPU crystal "pull" range and how critical are the caps, for e.g. USB FS
« Reply #12 on: February 21, 2024, 08:23:00 pm »
74HCU04 is a massive device, too, compared to others.  With ~5mA Icc and 10s of mS transconductance, it's well suited to low impedance filters and high drive powers.  Perhaps no surprise they give quite large values then, but interesting to also see sensitivity addressed.

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Offline faststoff

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Re: CPU crystal "pull" range and how critical are the caps, for e.g. USB FS
« Reply #13 on: February 22, 2024, 09:04:44 am »
Maybe the most practical way to qualify xtals is to do temperature tests with Rext values from zero to a "lot" and work out the margins.

As the appnote says, amusingly:



There is an obvious typo here; should be increase instead of decrease.


In my case, 15pF, the "capacitive reactance of CL2 is 420 ohms, but that is just the cap itself. The stray cap is on top. So if they reckon the divider formed by Rext and C2L2 should start at 2:1, I am in the right ballpark with 220R.

Their discussion of Rext is peculiar, yeah.  s/decr/incr/ is a fairly simple typo, if a somewhat glaring one.

There are generally two types of oscillator in common use: current-limited or biased amplifier style, and schmitt trigger (logic output) style.  The latter as you can guess, has 3.3V or whatever full scale output, so would drive considerable power into the crystal, and maybe overvolt the input pin even if the crystal withstands that power.  A series limiting resistor, usually around 1k, sets the source/termination impedance for the filter, and sets drive power to a reasonable level.

The other kind, the amplifier can be modeled as an ideal gm amp, i.e. a current-source output, and the series resistance can be ignored.

Why ST suggests a resistor, then, is somewhat mysterious.

Now, it may be that the biased MOSFETs operate in or near the triode region, so that the incremental output resistance is not actually very high, and then Rext acts as a current divider with that impedance.  So too, the gm decreases sharply as the input voltage leaves the Q-point (i.e., gm(Vin) has a peak near quiescent, and dropping fairly quickly off to the sides).  This nonlinearity might be employed by itself to limit operating amplitude, without any tuning at all; and, I think this is a very common mechanism in use.

Perhaps ST doesn't have tight enough process control for that stabilizing mechanism; or that they intend the user to have some amount of freedom, say to tune it for even very small (low power limit) crystals?  That additional level of constraint wouldn't be something they can account for (or, not very practically given other limits like pin Cstray), but with Rext, perhaps scope can be extended just a bit farther.

It could also be a cascode style output stage, where Zo is high, and Io is roughly a rounded-step function of Vin (more precisely, something like a tanh function, but probably a bit lumper from the sum effect of multiple stages' nonlinearity).  This still exhibits amplitude limiting (average gm decreases with increasing amplitude), but Rext would have little impact on it.  It may finally also be, that the internal/pin Cstray is high enough to add a pole with Rext, therefore reducing crystal power and loop gain; it will also affect loop stability, detuning it a little (which I suppose is to say, sensitivity is higher than just the straight impedance divider ratio would suggest, hence the relatively small values suggested).

Tim

Thanks for the insights!

Having recently gone through the process of actually measuring the drive level of two different ST designs, it seems like their internal architecture has changed somewhat over the years. For a device featuring STM32F103, I to had increase Rs significantly to lower the drive level of the crystal. Seems like the internal architecure is of a type driving the full available voltage out on the pin. For a device featuring STM32H7, the drive level was seemingly limited automatically by the on-chip hardware.
« Last Edit: February 22, 2024, 11:27:09 am by faststoff »
 

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Re: CPU crystal "pull" range and how critical are the caps, for e.g. USB FS
« Reply #14 on: February 22, 2024, 11:44:42 am »
Quote
Having recently gone through the process of actually measuring the drive level of two different ST designs, it seems like their internal architecture has changed somewhat over the years.


This is not a secret. In fact, ST is very clear about it in AN2867, see e.g. Table 6. HSE oscillators embedded in STM32 MCUs/MPUs.

JW
 
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Re: CPU crystal "pull" range and how critical are the caps, for e.g. USB FS
« Reply #15 on: February 22, 2024, 01:27:10 pm »
Quote
Having recently gone through the process of actually measuring the drive level of two different ST designs, it seems like their internal architecture has changed somewhat over the years.


This is not a secret. In fact, ST is very clear about it in AN2867, see e.g. Table 6. HSE oscillators embedded in STM32 MCUs/MPUs.

JW
You are absolutely right. My knowledge on the matter is limited, so from those numbers it is not immediately obvious to me that they imply the need for / not need for a resistor though :/
 

Offline peter-hTopic starter

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Re: CPU crystal "pull" range and how critical are the caps, for e.g. USB FS
« Reply #16 on: February 22, 2024, 03:30:13 pm »
How can I determine whether Gm(min)=5 is suitable for a given xtal?

Obviously whether it starts or not at all is the most important thing, and especially over temperature is the bit which can bite you the worst.



That appnote seems to be very old. They recommend all sorts of xtals for the STM8, and for the LSE (which is probably a tougher challenge to get right, due to watch xtal reluctance to work), but nothing for STM32 HSE.

It also gives an experiemental procedure for doing it, which seems really hit and miss. And the xtals actually available don't seem to come with the data needed to do the calculations.
« Last Edit: February 22, 2024, 04:18:55 pm by peter-h »
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Re: CPU crystal "pull" range and how critical are the caps, for e.g. USB FS
« Reply #17 on: February 23, 2024, 08:17:38 am »
All this BS is why I've given up on bare crystals and would rather use MEMS or crystal oscillator modules. Can sleep well at night with a fast time to market and negligible extra cost.
 
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Offline peter-hTopic starter

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Re: CPU crystal "pull" range and how critical are the caps, for e.g. USB FS
« Reply #18 on: February 23, 2024, 10:23:06 am »
Substantial extra cost; otherwise I agree :)

The interesting thing is that nobody has posted their results of a "proper" xtal evaluation, over a range of cap values and Rext, to find out where it stops working.

The most useful data is from PCB.Wiz, regarding the delta f due to cap variation.

I have a feeling that most people don't bother, copy some appnote / dev board for the values, and 99% of the time it works.

Back to cost of oscillators, typing e.g. this into Mouser
https://www.mouser.co.uk/c/?q=oscillator%2025mhz
yields a factor of about 5x on cost, but if you look for the cheapest you can find 1k pricing in the 60p region e.g.
https://www.mouser.co.uk/ProductDetail/ECS/ECS-3953M-250-BN-T-TR?qs=3Rah4i%252BhyCE7s0uJVfWw7A%3D%3D

But then if you are in serious production you can get xtals for 15p. Or < 10p for 10k+ for various chinese ones.

One could argue that 60p minus say 15p is not much, and mostly you would be right, but

- the cheap ones are chinese, no-name, rebranded by a Western company, and how do you know they have done it right?
- historically none were cheap
- there seem to be very few cheap ones
- supply current of 20mA could be an issue for some

I've used oscillators many times in the past, usually in the £2 sort of price range.

« Last Edit: February 23, 2024, 02:17:21 pm by peter-h »
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Re: CPU crystal "pull" range and how critical are the caps, for e.g. USB FS
« Reply #19 on: February 23, 2024, 09:42:22 pm »
But then if you are in serious production you can get xtals for 15p. Or < 10p for 10k+ for various chinese ones.
You also need to include the BOM and placement costs and PCB area costs of the two capacitors, and the cost of the lost pin.

lcsc lists oscillators from ~ 20c/100's with the 3225 package being the lowest price.
Crystals are 3~4c region, also with 3225 package being cheapest.

Not all MCUs have crystal osc support, the smaller pin count, lower cost ones often remove that item, thinking their calibrated RC osc is 'good enough' for most use cases, and an ExtOsc covers the others.

 
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Offline peter-hTopic starter

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Re: CPU crystal "pull" range and how critical are the caps, for e.g. USB FS
« Reply #20 on: February 24, 2024, 08:33:37 am »
You are right e.g. this one, from Kyocera so not a no-name chinese one, is under $0.30 1k+
https://datasheet.lcsc.com/lcsc/2201301300_Kyocera-AVX-KC3225K25-0000C1GE00_C1988954.pdf

Amazing!
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Re: CPU crystal "pull" range and how critical are the caps, for e.g. USB FS
« Reply #21 on: February 24, 2024, 09:10:04 am »
Substantial extra cost

Really? Come on, what is your CBOM, and how many equivalent hours did you spend saving $0.40 or so on *other* components/circuit designs?
 

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Re: CPU crystal "pull" range and how critical are the caps, for e.g. USB FS
« Reply #22 on: February 24, 2024, 01:24:02 pm »
In the audio applications, when the host and device clock domains are independent of each other, two isochronous pipes are used for downstream data transfer. One is for sample data transmission, the other (of the opposite direction) is for the buffer feedback, according to the usb class spec. It's obvious that without the feedback information, sooner or later, there will be a buffer issue in the device. But how soon? Although the worst time could be determined through the math, I once measured it, out of curiosity. The buffer on the device was of the capacity of 3-4 sample packets. The firmware waited for the buffer is falf-full before starting using it. On each overflow/underflow event, the buffer was re-initialized and the event was reported via the debug console. To my surprise, it was not unusual to wait for minutes between the events. With tens of different random computers, not just with one or a couple. The conclusion: the respective clocks are of almost similar frequency thanks to the physical properties of the quartz crystals. If the exact similarity is critical, then appropriate mitigation measures shall be taken. But if not, all that pf counts are seems of secondary importance.
 

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Re: CPU crystal "pull" range and how critical are the caps, for e.g. USB FS
« Reply #23 on: February 24, 2024, 05:19:31 pm »
So, to get back to the Q, what is the point of crystals when you can get an oscillator for $0.30?
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Re: CPU crystal "pull" range and how critical are the caps, for e.g. USB FS
« Reply #24 on: February 24, 2024, 06:34:37 pm »
So, to get back to the Q, what is the point of crystals when you can get an oscillator for $0.30?

Crystals are still cheaper  8)
Oscillators also have a higher icc unless the MCU puts them to sleep.
The YXC 110 series from Lcsc measure at ~1.5mA ( no load) so modern ones have improved from the generic 20 mA data sheets.
Also check the oscillator startup details on a scope.
The best are clean and running ~1ms, the worst (? Brand ) I tested looked like it oscillated at quite the wrong MHz before deciding to start properly. Enable of external clock to MCU too soon on that one, would be risky.
 


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