Creating a nested loop in ASM programming

[EENG]

Hallo

I am busy trying out the PIC KIT 1 to get familiar with these micros and ASM language. I ammended tutorial 2 that came with the evaluation PIC KIT 1. Its an example of a state machine. The tutorial  allows one to press a button on the board and after each button press, an one LED out of eight lights up. After each button press, the next LED lights up and so forth.

So basically I removed the button press detection in the SW and I decided to add a nested loop as shown below  (extracted portion of the code. The question will follow below):


;************************** VARIABLE DEFINITIONS ******************************

     cblock   0x20         
    Counter1
    Counter2
    Counter3
      endc



;************
;Init
;************
    clrf    Counter1
    clrf    Counter2
    clrf    Counter3
;***************************************************************************
; State_Machine
;        
;***************************************************************************

State_Machine
    clrwdt            ; clear Watch Dog Timer

    comf Counter1,f     ;set counter 1 to all 1's i.e. FFh. The letter f=1 in the p12f629.inc file
    comf Counter2,f
    comf Counter3,f

Loop1  decfsz Counter1,f

       ;Loop2 decfsz Counter2,f
             
       ;      Loop3 decfsz Counter3,f
       ;            goto Loop3
                   
       ;      goto Loop2
       
       goto Loop1


Question:
Can I do a delay in the form of a nested Loop1, Loop2 and Loop3 as shown above? When I inserted this into the code, it built ok but the delay does not work when I program it into the pic 12F675.

When I only use Loop1 (i.e. with Loop2 and Loop3 disabled by the semicolon ";" all 8 LED's light.
So the only conclusion I can make is that the Loop1 delay is to short and as a result the LED's are switching at a very fast pace....the result of which is that they appear to all be on continuously

The moment I activate Loop2 , all LED's are off and there is no sequential LED ON /OFF sequence.

I suspect that the nested loop is a violation in ASM programming?
      

[IanB]

I suspect that the nested loop is a violation in ASM programming?

If you code a nested loop in a language like C then it will be compiled down to a nested loop in the output code. So a nested loop can't be a violation of any programming rules.

Evidently you have some kind of logic error in your code, but I am not in a position to see what it is.

[8086]

Question:
Can I do a delay in the form of a nested Loop1, Loop2 and Loop3 as shown above?

Yes.

Here's a snippet from one of my projects

Code: [Select]

DELAY
MOVLW d'50'
MOVWF REG7
MOVLW d'45'
MOVWF REG6
MOVLW d'212'
MOVWF REG5
DECFSZ REG5,F
GOTO $ - 1
DECFSZ REG6,F
GOTO $ - 5
DECFSZ REG7,F
GOTO $ - 9
RETURN
This definitely works so if you use it as a guideline you should be good.

[Dazed+Confused]

Would this help?
http://www.golovchenko.org/cgi-bin/delay

[EENG]

Hallo
I looked at the site you mentioned below. Thank you for this information. I have two questions:

1. If the clock is 4MHz, then what is the time taken from one instruction to the next instruction?
For example...if you look at the code below, we have a startpoint (see arrow) and a finish point (see arrow). Common sense tells me that from "start" to "finish" is a simple 6 instruction cycle event.......so am I right in saying that each step is (1/4MHz) seconds? Is the time from "start" to "finish" = (6/4MHz) seconds?

start-->    movlw   0x03
   movwf   d1
   movlw   0x18
   movwf   d2
   movlw   0x02
finish--->   movwf   d3


Question 2. In the delay routine below, what exactly does the $ + 2 do? Am I right in saying that $+2 advances the instruction pointer (as I understand it) by two steps and as a result omits the instructions that it "jumped" over?



; Delay = 0.5 seconds
; Clock frequency = 4 MHz

; Actual delay = 0.5 seconds = 500000 cycles
; Error = 0 %

   cblock
   d1
   d2
   d3
   endc

         ;499994 cycles
   movlw   0x03
   movwf   d1
   movlw   0x18
   movwf   d2
   movlw   0x02
   movwf   d3
Delay_0
   decfsz   d1, f
   goto   $+2
   decfsz   d2, f
   goto   $+2
   decfsz   d3, f
   goto   Delay_0

         ;6 cycles
   goto   $+1
   goto   $+1
   goto   $+1

[mobbarley]

An 8bit pic's instruction cycle is the clock / 4. So for a 4 mhz clock you get an instruction every 1Mhz (1uS). The exception is a branch (goto) etc which takes 2x as long.  This is in your PICs data sheet.