Author Topic: Ethernet Implementation Project  (Read 1826 times)

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Offline shaunmTopic starter

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Ethernet Implementation Project
« on: October 04, 2016, 10:42:57 am »
Hi Everyone,

My name is Shaun and I'm currently in my final year of an engineering course. Part of any final year is an fyp or final year project (dissertation... whatever you want to call it). Anyway my subject is on the implementation of video transmission using 10G Ethernet (FYI Artix-7). After my own research as well as a few meeting with some University lecturers we have come to the conclusion that the best way to start is from the bottom up... that is comparing the OSI model with what is to be done and starting from the physical layer. Now, at the physical layer I know that Ethernet implements PMA/PCS (IEEE standard). My question is what's next, I'm stuck, is there any VHDL code that I can have a look at or can I just jump to the implementation of MAC since PMA/PCS is already found in an IP core. And if I should jump straight into MAC, what would be a good starting point?

Any help would be greatly appreciated... I'm still way ahead of schedule for this project so no worries.
 

Offline dmills

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Re: Ethernet Implementation Project
« Reply #1 on: October 04, 2016, 11:27:48 am »
IIRC xilinx have a SMPTE 2022-6 core as a stock part of the vivado library, and they have an IP core for 10G-E.

https://www.xilinx.com/products/intellectual-property/ef-di-smpte2022-56.html

I would start here, as SDI to and from 2022-6 should be straightforward, at least for a SDI-3G stream, 12G may be more interesting mostly because getting the serdes to meet timing gets fun up there.

Regards, Dan.
 

Offline Scrts

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Re: Ethernet Implementation Project
« Reply #2 on: October 04, 2016, 01:52:03 pm »
I only did a compressed stream over UDP packets, but in general yes - you begin at MAC level forming the packets from there. You add the IP header, UDP header and the rest of the data.
 


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