Extra pins? Why isn't my design fitting?

[gregallenwarner]

I'm writing some VHDL for an Altera EPM3064ATC44-10 (MAX3000A CPLD) using Quartus II 13.0. It's basically a shift register, with both parallel in/parallel out, serial in/serial out. I'm going to use it to interface a small microcontroller to a parallel SRAM chip via the uC's SPI bus.

The chip I'm using has 34 IO pins. By my count, I have 32 pins declared in the VHDL entity. However, when I try and compile the design, Quartus II fails, reporting 36 pins used out of an available 34. Where are these extra four pins coming from? I don't know the Quartus software well enough to know where to go to have it generate a report of all the pins it's trying to assign.

All I've done so far for manual fitting is placed my two clock signals and the OE (output enable) signal on the chip's global clock and OE pins. I've left everything else unassigned for the fitter to automatically place.

Here is my code:

Code: [Select]

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity shift_bus is
port (
addr : out std_logic_vector(17 downto 0);
data : inout std_logic_vector(7 downto 0);
ser_in : in std_logic;
ser_out : out std_logic;
oe : in std_logic;
sh_clk : in std_logic;
st_clk : in std_logic;
load : in std_logic
);
end shift_bus;

architecture arch_shift_bus of shift_bus is
signal addr_reg : std_logic_vector(17 downto 0);
signal data_out_reg : std_logic_vector(7 downto 0);
signal data_in_reg : std_logic_vector(7 downto 0);
signal set_signals : std_logic_vector(7 downto 0);
signal clr_signals : std_logic_vector(7 downto 0);
begin

-- Data lines output enable process
process (oe, data_in_reg)
begin
if (oe = '0') then
data <= data_in_reg;
else
data <= "ZZZZZZZZ";
end if;
end process;

-- Serial in shift process
process (sh_clk, ser_in)
begin
if (rising_edge(sh_clk)) then
addr_reg(17 downto 1) <= addr_reg(16 downto 0);
addr_reg(0) <= data_in_reg(7);
data_in_reg(7 downto 1) <= data_in_reg(6 downto 0);
data_in_reg(0) <= ser_in;
end if;
end process;

-- Address lines latch process
process (st_clk, addr_reg, data_in_reg)
begin
if (rising_edge(st_clk)) then
addr <= addr_reg;
end if;
end process;

-- Asynchronous parallel data load process (Generate SET signals)
process (load, data)
begin
for i in 0 to 7 loop
set_signals(i) <= data(i) and not load;
end loop;
end process;

-- Asynchronous parallel data load (Generate RESET signals)
process(load, set_signals)
begin
for i in 0 to 7 loop
clr_signals(i) <= not set_signals(i) and not load;
end loop;
end process;

-- Serial shift out process (and SET/RESET for asynchronous load)
process (sh_clk, set_signals, clr_signals)
begin
for i in 0 to 7 loop
if (set_signals(i) = '1') then
data_out_reg(i) <= '1';
elsif (clr_signals(i) = '1') then
data_out_reg(i) <= '0';
else
if (rising_edge(sh_clk)) then
if (i /= 0) then
data_out_reg(i) <= data_out_reg(i-1);
else
data_out_reg(i) <= '0';
end if;
end if;
end if;
end loop;
end process;

ser_out <= data_out_reg(7);

end arch_shift_bus;

EDIT: Nevermind, I see. I have to repurpose the JTAG pins if I want to fit this design to this chip. There are only 30 non-JTAG pins available. My bad.