Free ARM core for FPGA

[asmi]

(Almost) every modern FPGA has a hardware DDR memory controller nowadays so that doesn't really make a difference.

None of 7 series FPGAs have hardware memory controllers. Their fabric is fast enough to allow "soft" implementation of these controllers, so MIG can generate any configuration you require, and even several controllers at the same time. It does take quite a bit of logical resources though, for example DDR3L x16 controller takes about 8k LUTs and 10k FFs.

[asmi]

Not really.

This is not a fair comparison. How much is a Zynq version of A35T with four 6Gbps MGTs?
There is much better selection of devices in Artix family. If you come just short on resources of a small Zynq, your next option is waaay more money, while with Artix scales up quite nicely.

[NorthGuy]

Not really.

This is not a fair comparison. How much is a Zynq version of A35T with four 6Gbps MGTs?
There is much better selection of devices in Artix family. If you come just short on resources of a small Zynq, your next option is waaay more money, while with Artix scales up quite nicely.

Both Zynq and Spartans go to about 100K. With Artix'es the only device above 100K is A200T, but the experts say it should never be used:

https://www.digikey.com/product-detail/en/xilinx-inc/XC7A200T-3FFG1156E/122-1858-ND/3925786

There is no point going with this device, as Kintex-160 is about the same price, while it will give you double memory bandwidth and double transceivers speed.

[julianhigginson]

(Almost) every modern FPGA has a hardware DDR memory controller nowadays so that doesn't really make a difference.

Id be interested to know what device size and cost they start to appear at.
It's certainly not in any of the smaller (artix) xilinx FPGAs that are cheaper than zynqs.

[asmi]

Both Zynq and Spartans go to about 100K.

I'm not talking above - I'm talking below. Again - what is going to be Zynq version of A35 with 4 6Gpbs MGTs?

With Artix'es the only device above 100K is A200T, but the experts say it should never be used:

I meant it should never be used as a starting device, but it still is available as pin-compatible "size up" device in case design won't fit in A100 and it's too late to respin the board for completely new device.

[asmi]

Id be interested to know what device size and cost they start to appear at.
It's certainly not in any of the smaller (artix) xilinx FPGAs that are cheaper than zynqs.

None of 7 series FPGA devices do because it's possible to implement them in logic if required. The only reason Zynqs have it is because lots of memory is all-but required for the MPU to be useful.

[nctnico]

(Almost) every modern FPGA has a hardware DDR memory controller nowadays so that doesn't really make a difference.

Id be interested to know what device size and cost they start to appear at.
It's certainly not in any of the smaller (artix) xilinx FPGAs that are cheaper than zynqs.

Spartan6 for example.

[asmi]

Spartan6 for example.

The core provided only for Vivado as and such 7 series devices and above.

[NorthGuy]

(Almost) every modern FPGA has a hardware DDR memory controller nowadays so that doesn't really make a difference.

Id be interested to know what device size and cost they start to appear at.

It is in all 7-series devices. Except the controllers are not monolithic. Rather there's a set of undocumented components, such as various kinds of PHASERs, frequency references, undocumented clock routing, undocumented clock options for SERDES's, byteline handling hardware etc. Xilinx's MIG IP uses all this stuff (along with regular fabric and documented components) to build DDR memory controllers.

[nctnico]

Spartan6 for example.

The core provided only for Vivado as and such 7 series devices and above.

It is Verilog so I don't see any problems using a different tool. Someone else in this thread created a project using tools from a different manufacturer.

[ataradov]

It is Verilog so I don't see any problems using a different tool. Someone else in this thread created a project using tools from a different manufacturer.

It is actually not clear. The DesignStart FPGA may not give you full Verilog, it is possible that they've made an exclusive deal with Xilinx and provide a locked IP core.

I tried with DesignStart Pro (the only thing available at a time). It is still available, but it is not licensed for free commercial use, only for educational purposes.

The whole DesignStart started with university programs and was only accessible to students. And then RISC V came along and ARM ended up worried and extended the program to everyone. Plus added M3 core as well, the original DesignStart only had M0.

DesignStart FPGA has M1, which makes sense if you plan to keep in in a final FPGA-based product.

[langwadt]

Id be interested to know what device size and cost they start to appear at.
It's certainly not in any of the smaller (artix) xilinx FPGAs that are cheaper than zynqs.

None of 7 series FPGA devices do because it's possible to implement them in logic if required. The only reason Zynqs have it is because lots of memory is all-but required for the MPU to be useful.

and I'd expect a hard DDR memory controller to be a fraction of the die area needed to implement it in logic

[langwadt]

I guess how well it goes will depend on how easy it is to use the arm core(s) with your custom logic, and how easy it is to get to everything you need to from your code... if it's easy to generate good hw API, and integrate with good arm toolchains, maybe it's worthwhile sometimes, assuming the soft arm is similar in resource use to similar existing options. there's plenty of existing options for running processor cores in your digital logic for programatic applications when you need something like that, so for this to gain a share of that space alongside the solutions that everyone already uses and knows, you'd want to see some advantages rather than just arm brand recognition....

Seems to me that if you're considering one of these M1 or M3 cores to be the bulk of your design in a regular small FPGA like a Spartan or artix, well, you'd be far better off with microsemi smartfusion (or maybe even cypress psoc if the digital design requirements are simple enough...)

Also don't forget the big A series processor zynq (and the newer A53/R5 cored socs) has another big advantage over straight FPGA. It also has a dedicated DDR controller... Very valuable if you have an application that needs a lot of memory storage coupled closely to your digital hw design, like lots of FPGA applications seem to.

the integrated cpu + fpga never really took of until they changed from "fpga with a cpu core" to "cpu with an fpga"

[nctnico]

the integrated cpu + fpga never really took of until they changed from "fpga with a cpu core" to "cpu with an fpga"

IMHO this is also due to the previous CPU cores in Xilinx FPGAs being PowerPC based.

[Bassman59]

the integrated cpu + fpga never really took of until they changed from "fpga with a cpu core" to "cpu with an fpga"

IMHO this is also due to the previous CPU cores in Xilinx FPGAs being PowerPC based.

I don't blame the processor core in the Virtex 4 and 5 for issues with it.

I blame the awful EDK and the awful Xilinx peripherals.

[langwadt]

the integrated cpu + fpga never really took of until they changed from "fpga with a cpu core" to "cpu with an fpga"

IMHO this is also due to the previous CPU cores in Xilinx FPGAs being PowerPC based.

maybe that was also an issue, but having to add a bunch of stuff to a core just to get it to do something,
and unless you added the same stuff as everyone else you need you to build you own OS etc. doesn't make it easier

[asmi]

Back on topic...
It looks like the current build will only allow to use Keil to build software At least I couldn't make SDK to create an application project for CM1 - it doesn't let me reuse BSP project that I've created beforehand, but generating new one right in the wizard throws some errors. Hardware did build successfully though for my latest Artix board (I had to use MDM for UART as my board doesn't have dedicated UART port), but I don't want to bother with Keil as I would never be able to afford it anyway...
So I guess I will wait until they fix all that.

[NorthGuy]

and I'd expect a hard DDR memory controller to be a fraction of the die area needed to implement it in logic

That's exactly one of the reasons why Zynq's PS DDR2/DDR3 controller makes the built-in ARM cores much more effective.

BTW: Still waiting for you to describe the advantages of feeble soft M0 cores over built-in A9 cores of Zynq.

[mac.6]

easy: you don't need to roll full linux build to do simple microcontroller task

[ataradov]

easy: you don't need to roll full linux build to do simple microcontroller task

You can easily do bare-metal stuff with A9. No need for Linux at all.

[langwadt]

and I'd expect a hard DDR memory controller to be a fraction of the die area needed to implement it in logic

That's exactly one of the reasons why Zynq's PS DDR2/DDR3 controller makes the built-in ARM cores much more effective.

BTW: Still waiting for you to describe the advantages of feeble soft M0 cores over built-in A9 cores of Zynq.

huh? they are two totally different classes of cpus, if all you need is a small state machine programmable in C or assembly
M0 fits the bill, if you need processsing power and linux A9 fits 

[asmi]

BTW: Still waiting for you to describe the advantages of feeble soft M0 cores over built-in A9 cores of Zynq.

Really? I think they are obvious. Lower power consumption, easier to code for, better packages (Zynqs <30 only exist in 0.8 mm pitch packages, I prefer 1.0 mm ones for routing reasons). And since they take so little resources, you can fit 10 of them into A35. How much is 10-core Zynq?

[NorthGuy]

huh? they are two totally different classes of cpus, if all you need is a small state machine programmable in C or assembly
M0 fits the bill, if you need processsing power and linux A9 fits

If all you need is a small state machine, it's best programmed directly in HDL.

And since they take so little resources, you can fit 10 of them into A35.

Why would you trade FPGA for a dozen of ARM cores?

Using langwadt analogy, it's like getting a fighter jet, melting it down, and making 10 bicycles.

[bson]

And what's the purpose of building a soft M0 core in the fabric which cannot be achieved by the built-in A9 cores?

The A9 and your custom peripheral are going to sit at opposite ends of a bus, which is a shared resource and potential bottleneck, so often you're going to need to move any "thinking" to the peripheral end of the bus.   The question as I see it isn't what a soft M1 can do that the A9 in a Zynq can't, but rather what kind of applications it excels at where other techniques like DSP blocks or sprawling logic/LUTs don't work as well, are difficult to get to work right, or are grossly resource inefficient.  Or, where it can greatly reduce bus traffic; one such example might be a custom protocol bridge between two very different physical wires or networks.  Say also add a monitoring port - with a soft M1 all this can be done in a peripheral without the back-and-forth copies across the bus.  The M1 just interfaces directly to the transceivers, and has a control interface of higher level driver interactions (configurations, statistics, routing, error reporting, etc etc).  The reason to use a CM of course instead of any ofter soft core is software familiarity (software quality improves with familiarity), tool chain quality and familiarity, and potential for code reuse.  If you already have a protocol implementation in C/C++ with a long trusted history because you've used it in a bunch of projects already, then it's pretty sweet to just drop it into your soft core project and use without modification.  You'll just need to figure out the platform end of things, like retransmit timers etc.

[nctnico]

huh? they are two totally different classes of cpus, if all you need is a small state machine programmable in C or assembly
M0 fits the bill, if you need processsing power and linux A9 fits

If all you need is a small state machine, it's best programmed directly in HDL.

No. The turn-around time on a large FPGA design can be several hours compared to several seconds to recompile software. Sure you can do simulations but if you have real hardware 'in the loop' then that goes out of the window. No, I'm not talking external chips here but complicated external systems. Using software to solve a complicated problem is much quicker. One of the FPGA projects I'm responsible for takes at least 2 hours to build in a minimal setup. This has a softcore it is a lot quicker to change when doing algorithm & parameter tweaking.