SN74LS04
[url]http://www.ti.com/lit/ds/symlink/sn54ls04-sp.pdf]http://www.ti.com/lit/ds/symlink/sn54ls04-sp.pdf] [url]http://www.ti.com/lit/ds/symlink/sn54ls04-sp.pdf[/url]
SN74LS374
http://www.ti.com/lit/ds/symlink/sn54ls373.pdfSN74LS541
http://www.ti.com/lit/ds/symlink/sn74ls541.pdfAs I have stated many times for low address latch,
#1 74ls373 is best choice
#2 74ls374 with inverted clock will work with some costs down stream on low address. The costs here are less valid low address time & loss of when low address is valid. Adding parts it is possible to create a new low address valid, but you might not need to based on what is connected.
#3 The circuit with 74LS374 & 74LS541
state 2 The high Z time must be >0
State 4 is a mess
More chips might cure problem, but then you have poor design and more chips.
Here you are trying to switch outputs with zero time delay & with out putting old low address on bus again.
The best you could get is the two active outputs with same logic level.
A high Z state time could work but is not a good design.
Think about Bruce's two inverter fix.
From 74LS04 data sheet
max delay is 15ns so two inverters in series is 30ns
But typical is 9ns high & 10ns low for a total of 19ns
This is at load listed in data sheet. Less load could be faster.
Which time also effects the time I listed in last post.
So using typical timing changes times in my list, some places it gets better while others gets worse.
As stated above, the best outcome is still a bad design.
The resistors on 541 output is also a hack that can cause problems.
Best choice is to call this a bad design and pick #1 or #2 from above
For Good design you need to know when things are valid & not valid..
For a Z80, MREQ tells you two things, It's a memory access and supplies a time reference to when address became valid.
For NSC800 a lot of timing is based on fall of ALE. Time Reference to when address became valid is one of these.
So to stop messing around you need to know what chips you are going to try to use, what memory chips, what IO.
Then you need to look at the timing these chips need to function.
For a memory or IO read with the AD0-AD7 bus you have the NSC800 driving lines then the memory or IO driving and back to NSC800 driving. You need a high Z time between each change of drive.
For a memory chip this is OE.
For CPU this is normally RD.
Check the timing from the two data sheets.
Here the two High Z times must be >0ns
Note that there is a difference if the memory read is an OP code read or Data read.
You could have four High Z times.
Each timing requirement must be valid.
The RD signal, more times need to be verified.
You now have one pin done on memory chip, repeat for all pins.
Doing this detail work is much quicker then trying to find poor design problems with test equipment.