How far away would you place your bypass caps before you considered a problem?

[nctnico]

It doesn't because of the parasitic inductance. Look at an impedance/ESR versus frequency graph and you'll see the impedance/ESR doesn't keep dropping off. Instead impedance / ESR increase beyond the self resonance point.

 

pack it up, lock the thread.. how many times does Tim have to repeat the words ABSOLUTE IMPEDANCE IS WHAT THE IC RAIL SEES before you realize just how wrong/misleading/incorrect the above statement is, and how many new generations of engineers will it take to purge 1980's thinking.

Then come up with a graph that shows the real behaviour according to you. If I hook up an SMT capacitor to a VNA, I see the impedance going up above the resonance point. And that matches the graphs when I go to the capacitor manufacturer's website. Logical, because there is an inductor in series with the capacitor which starts to dominate the impedance at some frequency (just like a piece of trace and/or a via does). Ofcourse power distribution is more than the capacitors alone but you have to start with basic part behaviour and add the circuit board behaviour to it in order to reach the required impedance.

So what if the impedance is going up (or down for that matter)?

What's important is that the impedance is low enough.

That goes without saying  But the way you accomplish the impedance getting low enough is the million dollar question. At some point you simply run out of room to add more 10uf capacitors around a BGA package (not to mention leaving room for traces). So what to do then? What you see in practise is that various values and/or package sizes are mixed to reach a wide enough frequency range. Some of the designs I have worked on need <7 milli-Ohm up to 20MHz and <30milli-Ohm up to 100MHz on some power nets. The chip manufacturer (NXP in this case) is very specific about mixing capacitor values in order to meet the design criteria.

[uer166]

practise is that various values and/or package sizes are mixed

Holy f**king shit. You started the whole thing of "So with several values in parallel using the same package size, you get a low impedance" crap which is what everyone has been debunking, but somehow the goal posts have moved once again. Nobody in this thread has argued even once that you could not achieve a low wideband impedance with multiple case sizes and an optimal layout. Here is the homework you are unwilling to do:

Consider 3 0402 size caps: 1nF, 10nF, 100nF parallel, vs 3 100nF caps parallel. Which one gives best impedance at high frequency? I chose the following parts in KSIM since they are characterized:


I have derived the parasitics and re-simulated in LTSpice with the following well matching result:


And here is the comparison of 3 caps of different values and 3 caps of the largest:


Which one is better? Obvious answer: below 400MHz, the 100nF x3 is way better, above that, they are identical.

[nctnico]

practise is that various values and/or package sizes are mixed

Holy f**king shit. You started the whole thing of "So with several values in parallel using the same package size, you get a low impedance" crap which is what everyone has been debunking,

You are reading selectively. I already wrote that NXP is using 3 (or even more) different values in the same package size in order to get the impedance low enough for their iMX8MQ reference design. I'm not making it up. Feel free to comment on the reference design.

[temperance]

So what if the impedance is going up (or down for that matter)?

What's important is that the impedance is low enough.

The inductance for a 0603 10 nF capacitor with a resonant frequency of 50 MHz is about 1 nH. For a 0402 10 nF capacitor with a resonant frequency in the 100 MHz range the inductance is 250 nH.

Ignoring PCB layout inductance, one can safely assume the capacitor series inductance to be much lower than those of  bond wires found in IC's like SO, TQFP,....


Bond wire inductance tables for different packages:
https://www.ti.com/lit/an/snoa405a/snoa405a.pdf

BGA decoupling, no bond wires: you will need VIA's to connect those capacitors. One 0.1 mm via with a height of 1 mm is typical 0.8 nH or even more and a 0201 capacitor has an inductance around 200 nH.

Just to put things into perspective.

[T3sl4co1l]

That goes without saying  But the way you accomplish the impedance getting low enough is the million dollar question. At some point you simply run out of room to add more 10uf capacitors around a BGA package (not to mention leaving room for traces). So what to do then?

...You do nothing at all, of course.

What more could you do, anyway?

Probably the most graphic examples are those ancient, giant CPU hybrids -- IBM, and... SPARC??, among others?? -- where the power supply interconnect was multilayer PCB absolutely studded with ceramics to essentially make a loaded transmission line of extremely low impedance.

And those were only, what, 100s of MHz?  Very hungry, 3.3 (or even 5?) V, huge chips, butting into the limits of the relatively coarse process node they had at the time.

Many of those modules had wide body and even LGA ceramic chip caps on them, too, for the same reason we put them on interposers (or even die directly) today of course.  But they did it on metal-ceramic monster backplates, because PCBs couldn't possibly handle the number of signals and planes, impedances, tempco (expansion rate), etc. that these beasts demanded.

The trickery doesn't end there; PDN design extends quite far on-chip, to the extent that logic itself is designed carefully so that limited populations are switching all at once, in any given region, so that the say 90% of inactive transistors that cycle can act as bypass capacitors for the ones that are switching.  Chip designers aren't dummies, obviously; in particular, they know the limitations of their systems and environments.  You can make estimates for the characteristic impedance or stray inductance of wire bonding, or die attach (flip chip), the interposer, balls, etc.  You will find it's not simply difficult, but outright impossible to get low supply impedances, at the PCB, much beyond 100MHz or thereabouts.

You can certainly have effective bypassing higher than 100MHz -- indeed bypasses need not even be explicit components at the highest frequencies, but that's for RF amplifiers, where much higher impedances are seen (say 50 ohm ballpark), and the inductance of the return paths is integrated as part of the resonant circuit design.  No such advantage is had for extremely low impedance CPU supplies, which also need it low across the board, and the only way they can do that is with a staged bypass scheme, from PSU to chip-adjacent to onboard to within-die.

What I don't know, is whether embedded stuff generally does this, onboard (interposer, stacked-die, or sufficient as bare die), or how close it must be placed on PCB.  Datasheets never give impedance and frequency requirements, so we are all in the dark here, bickering about long shadows cast upon our walls.

That still leaves "best practice", which aims for low and stable impedance, which is easiest done with the larger values, small chips, and avoiding certain parallel combinations, staggered sizes, etc. as discussed in part above.  But don't be a damned fool about it.  Plenty of newbies throw together boards with poor bypassing, or even lacking planes entirely, and manage to do work with them.  They might be an EMC disaster, but only the worst are so bad they're entirely nonfunctional.

Personally, I suspect that, by combination of onboard capacitance and modest power consumption, most embedded MCUs (of more than modest frequency i.e. >= 100MHz; say, STM32F4 to F7 and similar) aren't very demanding, whether by way of a relatively high impedance limit (imagine, bypassing an MCU with a couple high-ESR electrolytics instead... but, that should indeed be possible with some parts!), or a relatively low frequency limit (say, onboard handles >50MHz so you only have to worry up til then).  The noise and jitter requirements are also rather banal, except for certain specific peripherals, which likely have isolated / separately filtered IO or VCCA domains anyway (ADC most obviously, but also Ethernet, USB, core clock (PLL), etc. may apply).

Even the most trivial specs, manufacturers never provide -- consider the capacitance of VDD to GND alone!  This is so easily measured, you can do it yourself; I'd be willing to bet you'll find many large-ish MCUs in the ~uF range.  Now that would be some interesting (and useful) context for PDN design, wouldn't it?

Related note: microSD cards are permitted up to 8.2uF onboard capacitance, good to know for hot plugging purposes.  Where's that capacitance coming from?  Integrated chip caps?  Or the chip itself?  Who knows...

Tim

[temperance]

What I don't know, is whether embedded stuff generally does this, onboard (interposer, stacked-die, or sufficient as bare die), or how close it must be placed on PCB.  Datasheets never give impedance and frequency requirements, so we are all in the dark here, bickering about long shadows cast upon our walls.

See my earlier post on typical modern 32Bit controllers. They have an on board LDO and decoupling is done on chip. Some older chips require a capacitor on the outside for stability while some don't require an external capacitor.

The external decoupling is more required for:
-The input of the LDO. (but not much information is given very often.)
-The transient current (di/dt) required by what has been connected to the GPIO pins.

Even the most trivial specs, manufacturers never provide -- consider the capacitance of VDD to GND alone!  This is so easily measured, you can do it yourself; I'd be willing to bet you'll find many large-ish MCUs in the ~uF range.  Now that would be some interesting (and useful) context for PDN design, wouldn't it?

Only the LDO is messing up your measurement for most 32bit micros.

[nctnico]

That goes without saying  But the way you accomplish the impedance getting low enough is the million dollar question. At some point you simply run out of room to add more 10uf capacitors around a BGA package (not to mention leaving room for traces). So what to do then?

What I don't know, is whether embedded stuff generally does this, onboard (interposer, stacked-die, or sufficient as bare die), or how close it must be placed on PCB.  Datasheets never give impedance and frequency requirements, so we are all in the dark here, bickering about long shadows cast upon our walls.

For microcontrollers such info is typically missing in the datasheet but you might be able to find an appnote (unless putting a 100nf capacitor withing a few mm of the power pin will just work). Whatever could be perceived as a hindrance to design a component in, gets burried in an application note. For SoCs the power impedance requirements are very well specified; but this info is in the hardware manual or an application note. BTW: If you want to see an interesting appnote on power supply routing & decoupling, get the hardware manual for the ESP32-S3  They use the trace impedance to seperate the various analog and digital power supplies.

[Someone]

You're right that it's generally better to use a single, large capacitor, rather than several smaller ones. It doesn't matter if it has a lower self-resonant frequency. It will have a lower impedance at higher frequencies, simply because it has a lower ESR.

I'm specifically not saying that, and framed the situation of a given number of (possibly specifically physically sized) capacitances. Through all this noise the important point keeps getting pushed away.

If you had a choice of capacitance in a given footprint, almost universally the larger capacitance produces the better result.

Which is far more practical than the "spread out capacitance values to have resonances everywhere" that keeps getting parroted. Trace and case parasitics are the dominant limitation to high frequency decoupling, which is what the OP asked about. So I'm trying to cut through all the rubbish here and point people to contemporary and accurate content on that. But a certain member has taken it upon themselves to attack anyone else's discussion on the matter, walking the goalposts way off into troll land.

[temperance]

Through all this noise the important point keeps getting pushed away.

An other important point missing is this discussion is that the PCB layout becomes very critical of you want to keep the PDN impedance below that of a small MLCC. It's better to take a very close look at the PCB layout than looking at infinitum into the impedance offered by some MLCC caps. After all, a BGA has only a limited number of GND and VCC connections for which you need a bunch of VIA's measuring about 1 nH each.

[nctnico]

Through all this noise the important point keeps getting pushed away.

An other important point missing is this discussion is that the PCB layout becomes very critical of you want to keep the PDN impedance below that of a small MLCC. It's better to take a very close look at the PCB layout than looking at infinitum into the impedance offered by some MLCC caps. After all, a BGA has only a limited number of GND and VCC connections for which you need a bunch of VIA's measuring about 1 nH each.

Indeed. Which is why I keep bringing up the fact that designers who must be using board level PDN simulation tools + board level verification (measurements) are mixing values in the same package size. I can't believe they do this just for fun. In power distribution the PCB itself is a component you can't leave out of the analysis (just like RF design).

[Simon]

So thinking about it a little, if you had a high power usage, that the BGA parts should preform “better” than the large LQFP parts in terms of how much closer you can get the bypass caps? Does anyone recommend BGA parts for that reason? I’ve never seen it.

The alternative is that 10mm isn’t going to hurt anything very little of it matters despite being a large topic of discussion.

I think it's price mostly Capacitance is physical, you can't wish it into a smaller space so making tiny silicon and then asking for a ton of bypass capacitance will not magically make it happen. I have never worked on anything with so many caps. What I tend to use is a micro controller where a 100nF is recommended on each power pin, on a 64VQFN this is a challenge as a analogue supply and digital supply pins are next to each other. Obviously on 0.5mm pitch you won't get the cap sideways to get positive rail and GND close to the chip. So I end up pointing the positive to the chip and rely on the ground plane to not have much inductance. They then recommend something ridiculous like 10µF on each rail, I don't even try to get these close, it's impossible with a 1206-1812 part size. I think these are desirable mainly as bulk capacitance on steroids ESR wise and are more for arse covering purposes, so I don't fuss too much about them. Generally they go behind one of the smaller ones on the same rail.

[temperance]

Indeed. Which is why I keep bringing up the fact that designers who must be using board level PDN simulation tools + board level verification (measurements) are mixing values in the same package size. I can't believe they do this just for fun. In power distribution the PCB itself is a component you can't leave out of the analysis (just like RF design).

The idea for the kind of PDN you are thinking about is to keep the impedance as constant as possible because any peak or valley is responsible for noise on the PDN network even if those peaks are below the required PDN impedance.

A tough subject on its own for which you will need pretty expensive software and equipment to verify final product performance. Did NXP go so far to develop a dev board? Maybe you can ask them or connect a network analyzer to the dev board if you've got one and post the result here.

Is it a good idea to follow the dev board schematic? No if the PDN on your own board is different.

[nctnico]

Indeed. Which is why I keep bringing up the fact that designers who must be using board level PDN simulation tools + board level verification (measurements) are mixing values in the same package size. I can't believe they do this just for fun. In power distribution the PCB itself is a component you can't leave out of the analysis (just like RF design).

The idea for the kind of PDN you are thinking about is to keep the impedance as constant as possible because any peak or valley is responsible for noise on the PDN network even if those peaks are below the required PDN impedance.

A tough subject on its own for which you will need pretty expensive software and equipment to verify final product performance. Did NXP go so far to develop a dev board?

I think they went this far. Typically these evaluation boards from serious manufacturers (like NXP, NVidia, TI) are used as golden standards. If you ask support to help fixing a problem using your own design, their first reply is to try and replicate the problem on their reference design. Getting access to some form of board level AC power integrity simulation for my own designs is high on my list though.

Maybe you can ask them or connect a network analyzer to the dev board if you've got one and post the result here.

I have an IMX8MQ eval board so I hooked it up to my LF network analyser for a (crude) S21 shunt measurement for the memory supply (which is amongst the more critical supplies):


This is from a IMX8-nano design I designed myself:


In both cases I tried to pick injections & pickup points at a bulk decoupling site that has many vias to both ground and the power plane with the injection point close to the power supply. Also note that the eval board uses 0201 sized parts where my own design uses 0402 parts. When converting the S21 attenuation to impedance, both designs are well within specs.

Is it a good idea to follow the dev board schematic? No if the PDN on your own board is different.

Yes and no. In the end the power connections on the package and the layout guidelines (like placing the DDR memory within a few mm of the SoC, layer use, stackup, etc) limit the possible routing strategies (assuming a capable PCB designer). Or put differently: if you follow the layout guidelines where it comes to component placement, layer use and stackup you are not likely to screw things up. OTOH, if you just get creative with the schematic, you are on your own.