Okay, bearing in mind that im still a beginner who is trying to learn, this is what my RAM looks like:
module ram
(
input [31:0] data,
input [11:0] addr,
input we, clk,
output [31:0] q
);
reg [31:0] ram[2**11:0];
reg [11:0] addr_reg;
initial
begin : INIT
integer i;
for(i = 0; i < 2**11; i = i + 1)
ram[i] = {32{1'b0}};
ram[0] = 47;
ram[1] = 512;
ram[513] = 3;
ram[514] = 512;
ram[515] = 18; //stack pointer 512
ram[516] = 74; //BIO
ram[517] = 0; //PIN0
ram[518] = 523; //addr
ram[519] = 72; //SIO
ram[520] = 0; //PIN0
ram[521] = 47; //JMP
ram[522] = 516; //addr
ram[523] = 70; //CIO
ram[524] = 0; //PIN0
ram[525] = 47; //JMP
ram[526] = 516; //addr
end
always @ (posedge clk)
begin
if (we)
ram[addr] <= data;
addr_reg <= addr;
end
assign q = ram[addr_reg];
endmodule
As far as did i RTFM, I read the manual for the development board I got, and ive looked at some verilog information, but thats basically it. Ive learned quite a bit just by looking at simple examples online.