I2C - maximum capacitance

[nForce]

Why is there a maximum capacitance of 400pF for I2C bus? Why do we increase capacitance when connecting devices on the bus?

[T3sl4co1l]

Pins have capacitance -- check the datasheet.

Tim

[rstofer]

Wire has capacitance, and inductance. 

I2C is typically a short range protocol but there are buffer chips to extend it.
https://www.nxp.com/docs/en/application-note/AN255.pdf

[rounin]

I think the maximum capacitance has to do with rise and fall time requirements, given the moderately weak pull up strength I2C has. Too much capacitance and the edges get too slow. I think there is a spec for how much current an I2C device is expected to sink which limits the fall time, although probably not as much as the (typical) 4k7 resistor limits rise time.

[Rerouter]

I should also mention its 400pf at 100KHz,

If you run the bus slower, you can cope with a lot more capacitance.

[eb4fbz]

Maximum capacitance depends on required speed and pull-up resistors. Capacitance is due to traces parasitics and devices pin itself.

[nForce]

Thanks

The pull-up resistor 2k connected to the line pulls the line high. So when the communication starts the SDA goes low, so the current flows to the ground?

I am just checking if I understand correctly.

[rstofer]

Thanks

The pull-up resistor 2k connected to the line pulls the line high. So when the communication starts the SDA goes low, so the current flows to the ground?

I am just checking if I understand correctly.

Yes

This is what is known as an Open Collector bus.  No device pulls the signals up, they only pull them down. Resistors pull the bus up.  This allows for a 'wired AND' connection where it is electrically possible for two devices to pull own simultaneously without damage.  The data will be corrupted but nothing will be damaged.

https://en.wikipedia.org/wiki/Wired_logic_connection#The_wired_OR_connection

[bson]

Why is there a maximum capacitance of 400pF for I2C bus?

It's set by the max current at the 100kHz clock.  If you run it at lower clocks you can have higher load capacitance.  A host controller may also be able to drive a higher load, but unless it states otherwise assume it can handle 400pF at 100kHz.  It may also be able to run up to several MHz at much smaller loads.

400pF is a lot...

[TomS_]

This allows for a 'wired AND'

Do you mean wire OR? Although in theory it operates more like NOR.

[eb4fbz]

Why is there a maximum capacitance of 400pF for I2C bus?

It's set by the max current at the 100kHz clock.  If you run it at lower clocks you can have higher load capacitance.  A host controller may also be able to drive a higher load, but unless it states otherwise assume it can handle 400pF at 100kHz.  It may also be able to run up to several MHz at much smaller loads.

400pF is a lot...

Not correct. I2C outputs are only able to sink current, and this current way higher than pull-up current. Rising slew rate is limited by pull-up current and bus capacitance, and this is what determines the maximum speed.

[Ian.M]

OTOH the minimum pullup resistance is set by the weakest device on the bus's max pulldown current and the pullup rail voltage.

[David Hess]

This allows for a 'wired AND'

Do you mean wire OR? Although in theory it operates more like NOR.

It is wired AND because if all inputs are high (true) then the output is high (true) but since the level are inverted to true is low on every input and output signal, it becomes wired OR where any low (true) input produces a low (true) output.  See the second example below.

It is called wired OR in ECL also but the outputs are "open emitters" with a pull-down resistor.

[Fungus]

The pull-up resistor 2k connected to the line pulls the line high. So when the communication starts the SDA goes low, so the current flows to the ground?

Yes.

PS: It depends on your wires but 2k is too much in my experience, I usually end up using 470 Ohms with Arduinos, etc.

The best way to choose a resistor is to look at the bus with an oscilloscope and make sure it's rising/falling properly. Adjust resistor as needed.

[bson]

Not correct. I2C outputs are only able to sink current, and this current way higher than pull-up current. Rising slew rate is limited by pull-up current and bus capacitance, and this is what determines the maximum speed.

You didn't think through this enough.  Sinking is driving, too.  The optimal pullup resistance is a function of the max drive current and capacitance, and is calculated to balance rising and falling transition times.   (I assume this is what you mean by "speed".)  The resistance is calculated from the bus properties.  What sets the upper limit on the clock period is the capacitance and drive current, or conversely what sets the upper limit on the clock period is the drive current and capacitance.  The resistance is a derived value that just is whatever you need it to be.