Lattice iCE40 Global Buffer placement question/error

[thexeno]

Hello,

I am using the iCEstick with the iCE40 FPGA, with the ICECube2 tool + Synplify pro.

I am getting a strange error in iCEcube2 when making the P&R, at the place stage:

Code: [Select]

Phase 4
I2712: Tool unable to find location for GB clockFeeder.clkPrescSig_RNIJ0DC2_0
Error during global Buffer placement
The error is related to a clock signal coming out from a prescaler and shared by multiple instances of my design. Apparently, it assign some global buffer option as reconize it to be a clock, and some how it does not know where to put the signal.

If this signal is applied to only one instance, it works.

Now, I was trying with Synplify Pro, since it is able to make all the chain, up to the P&R.

Now I have two possible solutions:

1. Counter measure this GB problem in iCECube2
2. Know why Synplify mess up with the pin assignment: seems to read another pin contraint file, different from the one created in ICECube2

Help

[julius123]

I can't believe it. After years and long after having sent emails to Lattice (I got really impertinent answers but no solutions) the GA (global assholes) of Lattice finally posted a workaround for this.

It is here and it worked for me.
http://www.latticesemi.com/en/Support/AnswerDatabase/5/7/1/5714

For Details how to do it (suggestion 1) go to the Symplify pro reference manual at
https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=&ved=2ahUKEwjg3qvm38XrAhUQqpQKHTPBDg4QFjAAegQIARAB&url=https%3A%2F%2Fwww.microsemi.com%2Fdocument-portal%2Fdoc_download%2F136665-synopsys-fpga-synthesis-synplify-pro-me-l2016-09m-2-attribute-reference-manual-for-libero-soc-v11-8&usg=AOvVaw0QISnevxK3KmoiZcyJ5BcK

and read sides 74 ff.
A vhdl example is  on side 77.

That's all???

My gosch, just stay away from Lattice.

Julius

[thexeno]

No way! Was worth the 4 years wait!
Thanks!

[hostile]

still useful information.  Got stuck on this for a couple hours  and then a search led me to a dead thread on this great forum.  thanks

[Simply4638]

For anyone having this problem:

Solution seems to have the following link now: https://www.latticesemi.com/en/Support/AnswerDatabase/5/6/9/5699

For sake of eternity:

During Placer process in iCEcube2, this error appears: "I2712: Tool unable to find location for GB Error during global Buffer placement". How can this error be removed?
According to our experts, the error is caused by Synplify Pro generating too many GB (Global Buffer). There are 2 solutions that will work as stated below:

1. The solution is to set the attribute below in your RTL:

/* synthesis syn_global_buffers = */;
This is better explained in Synplify Pro's help file.

2. The other way is to demote a GB in iCEcube2 Floor Planner view. (global tab at the left pane.)

First approach did not solve for me. If you read in the synopsis manual above, it states: "If you specify an integer less than 6, the software infers six global buffers".

You can also use "syn_noclockbuf" for individual signals.