Hy, I am new in this forum,
I have a problem and I want to know if somebody has do some workaround for this issue.
The issue is with RAM/ROM mapped in EBR with registered outputs, I know that Lattice has the IPxpress utility, but I do not want to use it, I want to use generic modules.
What I try to implement is this for ROM:
module rom #(
parameter ADDR_ROM_BUS_WIDTH = 14,
parameter ROM_PATH = "NONE"
) (
input clk,
input [ADDR_ROM_BUS_WIDTH-1:0] a,
output reg[15:0]d
);
(* ram_style="block" *)
reg [15:0] mem [(2**ADDR_ROM_BUS_WIDTH)-1:0];
initial begin
if (ROM_PATH != "NONE")
$readmemh(ROM_PATH, mem);
end
always @ (posedge clk)
begin
d <= mem[a];
end
endmodule
And this for RAM:
module ram #(
parameter ADDR_BUS_WIDTH = 13, /* < in address lines */
parameter DATA_BUS_WIDTH = 8,
parameter RAM_PATH = "NONE"
) (
input clk,
input we,
input re,
input [ADDR_BUS_WIDTH - 1:0] a,
input [DATA_BUS_WIDTH - 1:0] d_in,
output [DATA_BUS_WIDTH - 1:0] d_out
);
(* ram_style="block" *)
reg [DATA_BUS_WIDTH - 1:0] mem [(2**ADDR_BUS_WIDTH-1):0];
initial begin
if (RAM_PATH != "NONE")
$readmemh(RAM_PATH, mem);
end
always@(posedge clk) begin
if(we)
mem[a] <= d_in;
end
reg [DATA_BUS_WIDTH - 1:0]d_out_tmp;
always@(posedge clk) begin
d_out_tmp <= mem[a];
end
assign d_out = re ? d_out_tmp : 'bz;
endmodule
How can be seed are very generic modules for RAM and ROM implementations.
The Lattice Diamond simulate and synthesize this modules correctly (the project work perfectly on simulation), but when I upload the configuration, all memory with registered output give 0 at output.
When I implemented this two modules with unregistered outputs I have the expected values at output( for ROM ).
This two modules work perfectly on XILINX, but I need to port the project on single chip solution, and the only devices with internal nonvolatile memory configuration and cheap are those from LATTICE.
This two modules are integrated in MEGA/XMEGA open source core IP developed by me found here:
https://git.morgothdisk.com/MorgothCreator/XMEGA-CORE-IP-TST