I'm fairly new to FPGA's from a theoretical angle, I've always just taken the approach of iterating the design until it works. Although I've generally only done pretty simple stuff like SPI interfaces etc...
Currently I'm trying to get an SDRAM interface working on a Mach XO2. I have some verilog code from Hamsterworks which I have incorporated into my design and can simulate it just fine. I now want to correctly assign the setup and hold parameters for timing analysis so I can see how fast I can clock this (ideally I'd like to reach at least 133mhz).
I have a number of values from the datasheet such as address / RAS / CAS / etc... setup and hold times. I've tried setting CLOCK_TO_OUT with the setup and hold times (1.5 / 0.8 ns) but then get setup violations. Fine, so I set the clock offset to 0.5x (I'm forwarding the clock 180 degrees out of phase to clock out), but now I'm getting hold violations. It should be holding for 1 clock afaik as it's all registered on the positive clock edge, so I must have something setup wrong.
Any clues on setting up timing constraints like this correctly would be much appreciated as I've not been able to make much sense of any tutorials I've found with regard to this exact issue.
Just to clarify - what is it that you're looking for help with, the logic design issues of the timing, or getting them into constraint files to suit your tools?
Just to clarify - what is it that you're looking for help with, the logic design issues of the timing, or getting them into constraint files to suit your tools?
Its understanding how to setup the output constraints correctly in Lattice Diamond. I'm happy with the idea of pipelining to meet setup time at the expense of latency, but I dont understand why hold time isnt being met when the signals are latched at the posedge of the clock, so they will have a hold of half a clock cycle which is well in excess of the 0.8ns hold required. The clock skew of 180 degrees should solve both issues.
These are the timing constraints I want to enforce:
For my case for current testing, tCK=10ns (100MHz)
I'm specifically looking at the address lines at the moment as a starting point, so tAS=min 1.5ns, tAH=min 0.8ns
I'm outputting CLK at 180 degrees out of phase from my PLL derived 100MHz clock (from 13.3MHz source x7.5). So from my launch clock edge to posedge of the output CLK I should have 5ns in hand.
I want to know how I represent this in a CLOCK_TO_OUT constraint correctly.