I notice your other fallacious statements and misapprehensions have melted away. Good.
And what is it when it is simultaneously dealing with i/o from a USB link plus a front-panel, plus a motor, plus control-loop processing, plus data presentation processing, plus some DSP, plus... That's what hard realtime systems have to do.
MCUs don't work that way. Most of the work is dome by peripheral modules which ensure real-time operations. Peripheral does buffering, can do DMA if needed. This removes urgency from the CPU. CPU mostly organizes everything and often sits idle waiting for things to happen.
Ah, the old trap of thinking that hard realtime == fast. It doesn't. Hard realtime means guaranteed timing.
Your statement ignores the requirement for timing that is guaranteed by design, not by testing and measurement.
Two can play that (rather unenlightening) game, viz: presumably you are either using a tiny part of an FPGA and have an additional processor, or you have a very inefficient soft-processor in the FPGA. Either way is wasteful
FPGA don't work that way neither. Most of the stuff in FPGA is done by state-machines in parallel. The fabric is split between tasks and the tasks run pretty much independent using just as much resources as needed. Although, you can build soft cores and specialize them for the application, this is not necessary and often not needed.
BTW: "very inefficient soft-processor", such as Xilinx MicroBlaze can run circles around XMOS-cores.
You appear to be switching your definition of "efficient" between "low area" and "high performance" without bothering to tell people which you mean in any given statement.
There are many variants of MicroBlaze; which are you referring to?
Before implementing one in your design, what is the guaranteed cycle time (i.e. pre-layout)?
By what measure does the smallest (or largest) MicroBlaze run circles around the smallest (4 core) xCORE processor or largest (32 core)?
Xilinx Artix-7 wich can handle clock periods of 2ns starts from $25.
There are obviously cases where FPGAs will beat other technology; only a fool would think otherwise.
However, I'll note that the XS1 devices found in the £10 StartKit handle clock periods of 4ns - which is definitely encroaching on FPGA territory.
The newer xCORE200 devices have two tiles with up to 8 concurrent threads each. Each thread can run at up to 100 MHz, and threads may be able to execute 2 instructions in a clock cycle. Five threads follow each other through the pipeline, resulting in a top speed of 2000 MIPS (if all instructions dual issue), and a speed of at least 1000 MIPS (if all instructions are single issue)
That entirely depends on your application. Don't presume that your limited view of the world encompasses all applications.
My limited view of the world doesn't encompass applications. It encompasses principles and common sense. If you want to discuss applications, post the detailed description and specs for the application, and then we can discuss applications.
Common sense isn't common, and is irrelevant in significantly different situations.
Theory without practice is mental masturbation. Practice without theory is fumbling in the dark. The XMOS approach is strong in both theory (40 years old) and practice (30 years old) and specific implementation (10 years old).
You appear to be unaware of fundamental theory, so I'm unsurprised that you don't understand the relevant principles, and unsurprised that your "common sense" isn't applicable in this case.