The LTC2387-16 has a one or two lane DDR LVDS serial i/f which has to be clocked at 89MHz+ in two lane mode to achieve 15MSPS (data is sampled on both clock edges). What would be the easiest/cheapest way to interface it to an M3 or M4 Cortex MCU? I'm fairly flexible about the exact choice of MCU however.
The demo boards, DC2290A and DC2588A, use a Cyclone 3 EP3C5E144 which aren't exactly cheap. I've never done any FPGA development beyond some simple PALs several decades ago, so simplicity is desirable but cost is the most important issue. Ideally I prefer to avoid an FPGA/CPLD solution to avoid the learning time (though that could be interesting and useful for the future). Are there any low cost off the shelf shift registers with LVDS clock and serial data inputs and CMOS level outputs?
I wonder why LT and Analogue didn't make their parts easier to use? They could have provided a wider interface - a six bit CMOS interface would have used 1 less pin and could have interfaced directly to a (fast) MCU or via some jelly bean logic. I guess they assumed that an FPGA would be required anyway by most customers to process 15 MSPS of data. I see that TI at least are now using a 'Multi-SPI' interface on some newer convertors which can be up to 4 bits wide (although they aren't anywhere near 15MSPS).
I guess they assumed that an FPGA would be required anyway by most customers to process 15 MSPS of data.
How do
you intend to process 15MSPS of data?
Filtering and decimating mostly but also storing to a circular buffer until a the sampled data matches a trigger condition. A 180MHz STM32F4 or the 204MHz triple core LPC4370 should be able to handle the data processing and storage but obviously the filtering will be very limited (simple averaging may be enough) given only 12 to 15 cycles/sample! Generating the interface clock with the right frequency and phase using an timer may be a challenge though.
I have been looking for suitable LVDS logic parts - TI make LVDS deserializers but they aren't DDR and only go to 7 bits anyway (that I can find). LVDS to CMOS receivers and 74AC (or faster) shift registers/flip flops to convert to 18 bit parallel may be the answer. 15MSPS data can then be DMA'd from a GPIO port triggered by an MCU timer.
LVDS parts don't seem especially cheap though, and many are too slow anyway for this application - a lot it seems being geared to the LCD interface market. I wouldn't know where to start looking for a CPLD solution which could implement the deserializing and LVDS to CMOS translation at low cost and be easu to implement without a great deal of learning effort, hence the request for help here.
[EDIT] Clarified that processing of samples at 15MSPS will be very limited.
[EDIT 2] Corrected LPC5370 to LPC470
Just found the thread
https://www.eevblog.com/forum/projects/small-fpga-recommendation/The ICE40LP384-SG32, at around $1.5, QFN package looks almost perfect - supports LVDS, QFN32 package and a free and apparently simple develoment tool ICECube. With only 21 I/O pins it would have to deserialize to 9 bits parallel at 30MHz or 8bits at 45MHz. The STM32F405 GPIO operates up to 84MHz so that may be doable. Could this part do the job?
The XC9536XL-10VQ44C also suggested on that thread also looks good - except it doesn't appear to have LVDS.
Could I use the '$8 ICE40 Developer board' to prototype this (ie. does it support LVDS)?
@splin. NXP also has something they call
crossover processor. It's without flash and ram. and it runs at 500MHz. For code execution you can then ad almost unlimited size of QSPI flash and SDRAM. The pricing of cpu will be < 4$@100pcs
If you don't require a 16 bit ADC and 12 bits is enough, take a look at LPC4370
Yes it's an excellent ADC for the price - I actually have an Embedded Artists LabTool and LPC-Link2. I need 16 or 18 bits however.
Filtering and decimating mostly but also storing to a circular buffer until a the sampled data matches a trigger condition.
This is a perfect task for an FPGA. It can generate sample clock with internal PLL (note this will have more jitter than a good external PLL), do the LVDS interfacing, perform DSP (very good at fixed-point CIC, FIR filtering and decimation) and input/output to your MCU.
Storage to a circular buffer is quite possible with internal block RAM (multiple blocks can be ‘paralleled’ to get the quantity you need): how large a buffer do you need?
Filtering and decimating mostly but also storing to a circular buffer until a the sampled data matches a trigger condition.
This is a perfect task for an FPGA. It can generate sample clock with internal PLL (note this will have more jitter than a good external PLL), do the LVDS interfacing, perform DSP (very good at fixed-point CIC, FIR filtering and decimation) and input/output to your MCU.
Yes, but at what cost? An MCU is required anyway so an FPGA is just another cost - although doing some processing in an FPGA might save some money on the MCU. But how much more would an FPGA that can do some DSP (even if quite limited), with a decent size buffer of at least 64K bytes, cost compared to a $1.5 ICE40LP384-SG32 which looks like it could provide the DDR LVDS to parallel conversion?
Storage to a circular buffer is quite possible with internal block RAM (multiple blocks can be ‘paralleled’ to get the quantity you need): how large a buffer do you need?
64K minimum but 128K bytes would be good.
The cost balance depends on your application.
It looks like an ICE40UP5K-SG48 would set you back $12 NZ each ex DigiKey. (The crazy tiny BGA ones are $7.30 ea but hard to prototype). (You might get better pricing than DigiKey...)
So would it save you $10 of microprocessor sizing? The STM32F4 series are quite expensive... (And don’t forget the run time resource consumption!)
Alternatively you could use a larger FPGA and do the soft-core processor thing. But that way lies a man re expensive FPGA :-) (it’s funny how the FPGA marketing tends to go in that direction...)