Hi. I wasn't sure where to place this topic, but i think it suits here better then in the beginner lounge.
I am currently doing FPGA Video tutorials.The EEV-community showed big interest in this topic,so i decided to put my videos here. The videos are in my own style,so don't expect Dave-like content
.
Since i am going to do more tutorials, i will keep them in this thread.
Constructive feedback is appreciated.
Enjoy:)
Three suggestions:
1 - add audio. Currently this is just like reading a static web page, only worse. On the static web page I can absorb information faster, have a search function
and the fonts are not lossy
2 - you might want to make sure your video codec settings are optimized for text. As it is things are a bit blurry.
3 - add audio, because see 1)
Oh yeah, and provide a link to the source code. That way if someone want to try out your examples then they don't have to retype everything while staring at a poorly rendered font.
If I may ask, why VHDL over Verilog?
Sorry but I have to say this is a big fail.....
This is not how you develop for an FPGA.
Nothing about simulation..........,
Even with a very simple project there is not really any way you can continually fix bugs and rebuild the code ready to be loaded into an FPGA.
If I may ask, why VHDL over Verilog?
You can easily ask the reverse, why Verilog over VHDL?
I kind of like it. And loading straight into FPGA is not a bad idea either for small projects. Writing a testbench is quite an art in itself.
And VHDL vs Verilog is a flame war same as old as AVR vs PIC
And loading straight into FPGA is not a bad idea either for small projects. Writing a testbench is quite an art in itself.
Actually it is a bad idea that will bite you in the ass real fast. The real trouble is when it
seems to work, but is failing in subtle ways.
ok. I think i will answer every question one after another.
1.Why no voiceover?:
English is not my native language,. Since i have seen LOTS of video tutorials, where really bad pronunciation can ruin it all. And those official tutorials are from big companies like xilinix, altera, cypress etc. I always question myself why did they let this chinese/indian/korean girl/boy lead a tutorial.
That is why i decided to caption version.
Caption have also some advantages: you can place syntax there, write small examples, and overall you can always press space bar to pause the video, read what i "say" then read compare to my program.
Moreover if the viewer is also not native English speaker(which happens on youtube quite often), he/she will understand these tutorials much better.
2. Why VHDL?
I live in Germany. Everyone say that verilog is more common for USA/Australia, but in the rest of the world VHDL is more used.
As for me, i just like VHDL more, it si more self evident then verilog with his wires, always, etc...
3. Why no simulation?
In my tutorials I used simple codes like a few CASE and IF statements. You don't need a simulation for such easy stuff. Moreover i didn't want to overload the tutorial with simulations. The goal of my video were to show basics or how does procedure/function works. Sure more complex programs must be simulated, but for now it wasn't necessary.
English is not my native language,. Since i have seen LOTS of video tutorials, where really bad pronunciation can ruin it all. And those official tutorials are from big companies like xilinix, altera, cypress etc. I always question myself why did they let this chinese/indian/korean girl/boy lead a tutorial.
Don't worry. I bet that no one that comments on English skills would be able to do a better yob speakin an Indian language or Korean or German. If you know your native language well and get by in a second language, you are already ahead of the majority of youtube users.
I don't give a damn, as can be experienced in
video
I agree, but i want to make my videos international friendly, so everyone can understand it.
Are you from Switzerland:)
Are you from Switzerland:)
hey, the flag of my country is next to my avatar. Learn your geography
ah, didnt notice the flag:)
1.Why no voiceover?:
English is not my native language,. Since i have seen LOTS of video tutorials, where really bad pronunciation can ruin it all. And those official tutorials are from big companies like xilinix, altera, cypress etc. I always question myself why did they let this chinese/indian/korean girl/boy lead a tutorial.
That is why i decided to caption version.
Caption have also some advantages: you can place syntax there, write small examples, and overall you can always press space bar to pause the video, read what i "say" then read compare to my program.
Moreover if the viewer is also not native English speaker(which happens on youtube quite often), he/she will understand these tutorials much better.
2. Why VHDL?
I live in Germany. Everyone say that verilog is more common for USA/Australia, but in the rest of the world VHDL is more used.
As for me, i just like VHDL more, it si more self evident then verilog with his wires, always, etc...
3. Why no simulation?
In my tutorials I used simple codes like a few CASE and IF statements. You don't need a simulation for such easy stuff. Moreover i didn't want to overload the tutorial with simulations. The goal of my video were to show basics or how does procedure/function works. Sure more complex programs must be simulated, but for now it wasn't necessary.
1. Also assists people that are Deaf and Hard of Hearing
2. My University in Australia teaches VHDL so it possible some US based engineering firms have brought along Verilog and is now considered Australian. I wont really know until I finish Uni.
3. Simulation are good engineering practice now-a-days, it is taught even in the simplest configurations.
You can use a text-to-speech program to add a voice, even if it's not yours.
Sorry but I have to say this is a big fail.....
This is not how you develop for an FPGA.
Nothing about simulation..........,
Even with a very simple project there is not really any way you can continually fix bugs and rebuild the code ready to be loaded into an FPGA.
Rubbish. It is entirely feasible (and sometimes even quicker) to write and debug FPGA designs without going near a simulator.
Most FPGA projects will be interacting with external devices and interfaces, which will be difficult and/or time-consuming to emulate in the simulator, and prone to errors in translation.
It gets harder on larger projects due to compile time, but even then, by including plenty of debug functionality you can implement and test multiple incremental steps on each compile cycle.
Sorry but I have to say this is a big fail.....
This is not how you develop for an FPGA.
Nothing about simulation..........,
Even with a very simple project there is not really any way you can continually fix bugs and rebuild the code ready to be loaded into an FPGA.
Rubbish. It is entirely feasible (and sometimes even quicker) to write and debug FPGA designs without going near a simulator.
Most FPGA projects will be interacting with external devices and interfaces, which will be difficult and/or time-consuming to emulate in the simulator, and prone to errors in translation.
It gets harder on larger projects due to compile time, but even then, by including plenty of debug functionality you can implement and test multiple incremental steps on each compile cycle.
Although I generally like using ModelSim whenever possible, I can understand this point of view perfectly. Quartus has a very good SignalTap logic analyzer which lets one to look inside the FPGA in real time. It uses some logic and block RAM to perform its task and communicates via JTAG. Sometimes one needs to put some attributes to signals to prevent optimizations so one can more easily look at things, but that is relatively minor thing.
There are cases where using simulator is simply not feasible. For example I have worked on frequency estimation algorithm which ran at modest 80 MHz and processed input data at rate of 80 kHz. As settling time was in order of seconds when input frequency was low (<10 Hz), using a simulator was out of the question as it would have taken a very long time to simulate. Only practical way to test that was to use a real FPGA with real data. The input data was non-trivial also, so using simulation would have needed to first capture the input data in some way (not trivial either).
Regards,
Janne
+1 for VHDL at university in Australia.
I bought one of those basic Cyclone II breakout boards (basically breaks out all pins, has a few leds, the eprom, and clock source) and an altera MAX II clpd board. I have been meaning to learn a bit more about FPGAs so I'll check out your videos
(also thanks to mike for those ipod lcd videos, reminded me to look at fpgas again
)
Ok, i gave it a try, and put my voiceover on the second tutorial.
It took me much more time then expected since i was hearing the right pronunciation of every third word in wiktionary.
Well, the result is better then i thought.
I think i still have to work on pronunciation and intonation, right now my voiceover is pretty influenced through HowDoesItWorks Discovery series, but i will work on it:)
Much better
I didn't have much trouble with understanding you. The few times I had any problems, a quick look down at the caption was all it took. But with the voiceover I was able to follow what you were actually doing much more closely, and the video was much more enjoyable that way.
Nice tutes, but i find the music distracting. I couldn't watch it towards the end.
Still not my favorite tutorial style for this kind of subject, but an improvement over the previous ones.
Lose the distracting music and you just made another improvement.
Hm, i don't find this music distracting. I actually coding while hearing such kind of music....=)
Hm, i don't find this music distracting. I actually coding while hearing such kind of music....=)
Oh if only you were the target audience of your own videos.
I found it distracting, but maybe other people find the music helpful. Only more feedback will tell.
Sorry but I have to say this is a big fail.....
This is not how you develop for an FPGA.
Nothing about simulation..........,
Even with a very simple project there is not really any way you can continually fix bugs and rebuild the code ready to be loaded into an FPGA.
Rubbish. It is entirely feasible (and sometimes even quicker) to write and debug FPGA designs without going near a simulator.
Most FPGA projects will be interacting with external devices and interfaces, which will be difficult and/or time-consuming to emulate in the simulator, and prone to errors in translation.
It gets harder on larger projects due to compile time, but even then, by including plenty of debug functionality you can implement and test multiple incremental steps on each compile cycle.
Sorry complete nonsense. Compile times for even a fairly small design can be upward of 30 minutes.
your method is clearly unprofessional BECAUSE you would not have any test benches or methods to PROVE the logic, what exactly WOULD your testing method be..... oh wait.... realtime non- traceable and non-reproducible.
Good luck on 'real time' testing of a USB or GMII,RGMII design. just love to see you get that bandwidth over a JTAG connection.
go READ up on WHY VHDL was designed, also go read up on Software, logic testing for reliability.