/*
* Nixie_Clock_REV2_0_0.c
*
* Created: 27/06/2013 23:12:18
* Author: carbon dude oxide
*/
#define F_CPU = 20000000UL;
#include <avr/io.h>
#include <avr/interrupt.h>
#include <avr/delay.h>
double nixieSupplyDutyCycle = 0;
int powerSaveMode = 0x00;
int main(void)
{
//i/o declaration
DDRA = 0xFF; //set port A i/o (all outputs) Digits 1-2
DDRB = 0x80; // set port B i/o outputs:PB7 inputs:PB1-PB6
DDRC = 0xFF; //set port A i/o (all outputs) Digits 3-4
DDRD = 0xFF; //set port A i/o (all outputs) Digits 5-6
DDRE = 0xFF; //set port A i/o (all outputs) Digits 7-8
//PWM timer stuff.
TCCR2A = (1 << COM2A1) | (1 << WGM21) | (1 << WGM20); // set to fast PWM and mode.
TIMSK2 = (1 << TOIE2); // set to run interrupt when timer overflows
OCR2A = ((nixieSupplyDutyCycle/100)*255); //work out duty cycle
sei(); //set up external interrupts;
TCCR2A |= (1 << CS20); // set pre-scaler to 1. and start timer
while(1)
{
//TODO:: Please write your application code
}
}
//interupt service
ISR(TIMER2_OVF_vect_num) //interupt for timer 2 - for nixie voltage supply modulation at night or low power mode.
{
OCR2A = ((nixieSupplyDutyCycle/100)*255); //work out duty cycle as it may change mid code.
}
#define F_CPU = 20000000UL;
That's seriously wrong. You probably want:#define F_CPU 20000000UL
#define creates a text substitution at the pre-processor level; if there were a calculation later that looked liketicks = F_CPU/256L;
(which is not unlikely), it would have expanded toticks = = 20000000UL;/256L;
which is unlikely to compile, much less do the right thing.You know, back when I did a lot more programming I'd have immediately caught those things. Guess it's not quite like riding a bicycle...
Two-wire mode. Uses SDA (DI) and SCL (USCK) pins(1).
The Serial Data (SDA) and the Serial Clock (SCL) pins are bi- directional and uses open-collector output drives. The output drivers are enabled by setting the corresponding bit for SDA and SCL in the DDR Register.
When the output driver is enabled for the SDA pin, the output driver will force the line SDA low if the output of the Shift Register or the corresponding bit in the PORT Register is zero. Otherwise the SDA line will not be driven (i.e., it is released). When the SCL pin output driver is enabled the SCL line will be forced low if the corresponding bit in the PORT Register is zero, or by the start detector. Otherwise the SCL line will not be driven.
The SCL line is held low when a start detector detects a start condition and the output is enabled. Clearing the Start Condition Flag (USISIF) releases the line. The SDA and SCL pin inputs is not affected by enabling this mode. Pull-ups on the SDA and SCL port pin are disabled in Two-wire mode.
Two-wire mode. Uses SDA and SCL pins.
Same operation as for the Two-wire mode described above, except that the SCL line is also held low when a counter overflow occurs, and is held low until the Counter Overflow Flag (USIOIF) is cleared.
* Created: 27/06/2013 23:12:18
* Author: carbon dude oxide
*/
#define F_CPU 20000000UL
#define DS1307Address 0x68
#define SLA_W 0x69
#define SLA_R 0x68
#define DATA 0x00
#include <avr/io.h>
#include <util/twi.h>
int main(void)
{
while(1)
{
//TODO:: Please write your application code
}
}
void writeTimeToDS1307(void)
{
TWCR = (1 << TWINT) | (1 << TWSTA) | (1 << TWEN); //enable I2C and request start command
while (!(TWCR & (1 << TWINT))); //wait until start command has been sent
//some form of bit check / verification
TWDR = SLA_W; //load address and read/write bit into TWDR register
TWCR = (1 << TWINT) | (1 << TWEN); // clear TWINT and send data packet
while (!(TWCR & (1 << TWINT))); //wait until acknowledge is received
//some form of bit check / verification
TWDR = DATA //load data to be sent into TWDR register
TWCR = (1 << TWINT) | (1 << TWEN); // clear TWINT and send data packet
while (!(TWCR & (1 << TWINT))); //wait until acknowledge is received
//some form of bit check / verification
TWCR = (1 << TWINT) | (1<< TWEN) | (1 << TWSTO); //send stop command
}
/*
* NixieTubeClockRev2_0_1.c
*
* Created: 30/06/2013 16:58:31
* Author: carbon dude oxide
*/
#define F_CPU 20000000UL
#define DS1307_R 0xd0
#define DS1307_W 0xd1
#define second 0x00; //current seconds 0-3 bit is second 4-6 bit is 10 second 7 is low
#define minute 0x00; //current minutes 0-3 bit is minute 4-6 bit is 10 minute 7 is low
#define hour 0x00; //current hours 0-3 bit is hour 4-5 bit is 10 hour 6 bit is 12/24 hour 7 is low
#define day 0x00; //current day 0-2 bit is day 3-7 is low
#define date 0x00; //current date 0-3 bit is date 4-5 is 10 date 6-7 is low
#define month 0x00; //current month 0-3 bit is month 4 bit is 10 month 5-7 is low
#define year 0x00; // current year 0-3 bit is year 4-7 bit is 10 year
#define second_W 0x00; //temporary second to write
#define minute_W 0x00; //temporary minute to write
#define hour_W 0x00; //temporary hour to write
#define day_W 0x00; //temporary day to write
#define date_W 0x00; //temporary date to write
#define month_W 0x00; //temporary month to write
#define year_W 0x00; //temporary year to write
#define control_W 0x10; //set RTC to output a 1Hz pulse on SQW/OUT pin to write
#include <avr/io.h>
#include <avr/interrupt.h>
#include <util/delay.h>
#include <util/twi.h>
int main(void)
{
TWBR = 0x17; // set bit rate register to 23 to reduce the SCL to 100KHz
while(1)
{
//TODO:: Please write your application code
}
}
void ERROR()
{
//TWCR = (1 << TWINT) | (1 << TWEN) | (1 << TWSTO);
}
void updateTime()
{
TWCR = (1 << TWINT) | (1 << TWSTA) | (1 << TWEN); //send start condition
while (!(TWCR & (1 << TWINT))); //wait until start condition has been sent
if ((TWCR & 0xF8) != TW_START) ERROR(); //if the status register is not TW_START go to error
TWDR = DS1307_W; //load write address into register
TWCR = (1 << TWINT) | (1 << TWEN); //send address data packet
while (!(TWCR & (1 << TWINT))); //wait until ACK/NACK is received
if ((TWSR & 0xF8) != TW_MT_SLA_ACK) ERROR(); //has data packet been acknowledged? if not goto error.
TWDR = second_W; //load seconds to be written
TWCR = (1 << TWINT) | (1 << TWEN); //send data packet
while (!(TWCR & (1 << TWINT))); //wait until ACK/NACK is received
if ((TWSR & 0xF8) != TW_MT_SLA_ACK) ERROR(); //has data packet been acknowledged? if not goto error.
TWDR = minute_W; //load minutes to be written
TWCR = (1 << TWINT) | (1 << TWEN); //send data packet
while (!(TWCR & (1 << TWINT))); //wait until ACK/NACK is received
if ((TWSR & 0xF8) != TW_MT_SLA_ACK) ERROR(); //has data packet been acknowledged? if not goto error.
TWDR = hour_W; //load hours to be written
TWCR = (1 << TWINT) | (1 << TWEN); //send data packet
while (!(TWCR & (1 << TWINT))); //wait until ACK/NACK is received
if ((TWSR & 0xF8) != TW_MT_SLA_ACK) ERROR(); //has data packet been acknowledged? if not goto error.
TWDR = day_W; //load days to be written
TWCR = (1 << TWINT) | (1 << TWEN); //send data packet
while (!(TWCR & (1 << TWINT))); //wait until ACK/NACK is received
if ((TWSR & 0xF8) != TW_MT_SLA_ACK) ERROR(); //has data packet been acknowledged? if not goto error.
TWDR = date_W; //load date to be written
TWCR = (1 << TWINT) | (1 << TWEN); //send data packet
while (!(TWCR & (1 << TWINT))); //wait until ACK/NACK is received
if ((TWSR & 0xF8) != TW_MT_SLA_ACK) ERROR(); //has data packet been acknowledged? if not goto error.
TWDR = month_W; //load months to be written
TWCR = (1 << TWINT) | (1 << TWEN); //send data packet
while (!(TWCR & (1 << TWINT))); //wait until ACK/NACK is received
if ((TWSR & 0xF8) != TW_MT_SLA_ACK) ERROR(); //has data packet been acknowledged? if not goto error.
TWDR = year_W; //load years to be written
TWCR = (1 << TWINT) | (1 << TWEN); //send data packet
while (!(TWCR & (1 << TWINT))); //wait until ACK/NACK is received
if ((TWSR & 0xF8) != TW_MT_SLA_ACK) ERROR(); //has data packet been acknowledged? if not goto error.
TWDR = control_W; //load control data to be written
TWCR = (1 << TWINT) | (1 << TWEN); //send data packet
while (!(TWCR & (1 << TWINT))); //wait until ACK/NACK is received
if ((TWSR & 0xF8) != TW_MT_SLA_ACK) ERROR(); //has data packet been acknowledged? if not goto error.
TWCR = (1 << TWINT) | (1 << TWEN) | (1 << TWSTO); // initiate stop command
}