Author Topic: Need help to configure TFT display  (Read 315 times)

0 Members and 1 Guest are viewing this topic.

Offline udhay_citTopic starter

  • Contributor
  • Posts: 12
  • Country: in
Need help to configure TFT display
« on: April 03, 2025, 06:21:45 am »
Hi,
we are planning to use a 5" capacitive touch display with Renesas RA8D1 microcontroller. The current version product we completed with an onboard HMI display from Nextion (NX8048P050_011). We are not satisfied with the touch response and display quality, so we are looking for a better display solution.

The RA8D1 microcontroller has the provision for 2 lane MIPI interface but unfortunately there is no display in the market for 5" 2 lane MIPI interface, so we decided to use ICN6211 MIPI to RGB bridge IC. The screen capture of ICN6211 configurator is attached here.

I need to input the "Basic settings" parameters to get the I2C configuration file. I'm not familiar with the RGB LCD display interface, so please help us to understand the setting for our specific display module.

Please suggest a suitable values for the below parameter which is suitable for our LCD display(datasheet attached)

HFP
HSYNC
HBP
VFP
VSYNC
VBP
RGB clock (in MHz)
RGB clock phase adjustment - options are 0, 1/4, 1/2, 3/4
 

Offline Nominal Animal

  • Super Contributor
  • ***
  • Posts: 7544
  • Country: fi
    • My home page and email address
Re: Need help to configure TFT display
« Reply #1 on: April 03, 2025, 08:40:53 am »
See page 15. Timing characteristics.

The defaults are
    RGB clock = 25 MHz
    HFP   = Thfp = 8    (Horizontal Front Porch)
    HSYNC = Thw  = 4    (Horizontal sync pulse Width)
    HBP   = Thbp = 8    (Horizontal Back Porch)
    VFP   = Tvfp = 8    (Vertical Front Porch)
    VSYNC = Tvw  = 4    (Vertical sync pulse Width)
    VBP   = Tvbp = 8    (Vertical Back Porch)
For explanations of these names, see Wikipedia Horizontal blanking interval and Vertical blanking interval articles.  Horizontal values are specified in terms of the RGB clock cycles, and vertical timings in number of full horizontal scan lines.

Those defaults yield a horizontal period of 816 cycles and 496 scan lines, so 25000000/(816×496) ≃ 61.8 Hz referesh rate.  All of the above values are ranges, so they can be tuned if needed.

The RGB clock phase adjustment refers to when the display samples the parallel bus with respect to the clock.  According to ICN6211 specification v0.4, phase 0 matches the display expectations.  So try using 0 for RGB clock phase.  (All other clock phases will at least occasionally glitch.)
 
The following users thanked this post: udhay_cit


Share me

Digg  Facebook  SlashDot  Delicious  Technorati  Twitter  Google  Yahoo
Smf