For the interface, i will use a DDIO. with a dual buffer that will hold the current lower nibble and upper nibble. On rising edge, i will update my upper nibble and send my lower nibble, and on falling edge, i will update my lower nibble and send the upper nibble. For the clock, i will use a pll to shift it a little bit. 2 IP core : PLL and DDIO. I just finished doing the test packet (although, just a simple test like you, not the full application with LVDS). But now, the compiler don't like my const array. It say i got error at the ' symbole. : reg [some:size]someRegisterName[some:size] = '{lot of nibble}
So now its more the verilog syntax. I use this project to also learn verilog. The artyx board you are using is pretty nice by the way. Most modern terasic board either pack lot of feature, but with everything interesting (SD card, ethernet...) connected to the HPS (DE1-soc, DE0-nano-SoC), or are very minimalist(DE0-nan0) or costly (DE2-115, got ethernet and all other feature). Their DE1 was perfect, it got everything connected to its SoC (altought lacking ethernet, but got everything else), but its outdated, won't work with newest quartus. If only they could make an updated DE1 non-SoC, like they did with the DE2 (DE2-115). I got a nice book about SoC with FPGA (not arm SoC, but softcore SoC with nios II). The book was made for DE1. If i get the DE1-SoC, i could follow the whole book except for sram part, the green led part, and the sd card part(since its connected to the ARM). But for the sd card and the 8 lacking green led, i will (if i get the board) make a pcb (and use that occasion to learn kicad) with micro sd and green led, and even some other nicy (maybe an esp8266 and a bluetooth). But sram is not that easy to add on another pcb. Not trough normal header, too much capacitance, length, noise... At least, i could do 90% of my book.
But on the digilent side, altought their board got less stuff, they got two affordable recent technology board with ethernet NOT connected to a processor (ARM). Like the artyx you are using, or the nexys 4(with academic discount). But getting an altera board with ethernet would be more nice since I could do a full nios II learning path.
Unfortunately, I can get an academic discount, but shipping it here, import fee and ... will cost more than what I save with my academic discount. I wonder if I could get my academic discount trough local distributor like digikey or mouser.
Any suggestion of nice peripheral i could add to a DE1-SoC to enhance my overall experience and learning?
Now I am pretty confident of the success of my project.