The problem with most FPGA solutions come when you need to implement an algorithm that has loops with data dependencies in them.
In many cases we use loops in software as a short hand notation, e.g. if you have a FIR filter. In that case a simple loop can multiply input data and a filter coefficient, and add the result to an accumulate register. A typical implementation on a computer may do this by calculating intermediate sums 1 by 1, thus expanding the loop in time.
If you want to synthesize a fixed-width FIR filter, you can essentially write the same code in VHDL. However, if you were to write such a for loop straight away in a process, it would instantiate an multiplier and adder for each single tap, thus expanding the loop in space.
Of course you can also create a description that expands in time, but you would need to describe what happens across the multiple cycles with some extra registers/state.
This makes FPGA's very unattractive for parsing XML or JSON protocols, as there are many loops in such a system, often requiring intermediate results from other loops. In addition one cannot use recursion, so alternative implementations often then require more loops.
You would either expand massively into space or need to keep track of every single state that needs to be carried over from clock cycle to clock cycle.
For sure anything is possible, if it sufficiently constrained to not expand into infinite hardware. Additionally I doubt it would be much fun writing such a thing in a language as VHDL. I would consider writing such a system in a higher level language like
Clash, as it's very similar to functional programming. However even in that case it would be no trivial task.