14% accuracy clock for UART ok.
Why 14?
The typical uart transmission takes 10 bites - start (0), 8 bits of data, and stop(1), each of which takes 1 baud.
Not counting the stop bit, the worst byte is the last data byte which is transmitted between 8.0 and 9.0 baud distance from the beginning of the byte. The best way is to sample it in the middle 8.5 baud from the beginning.
If you're by 14% earlier, you'll be sampling at 8.5 - 14% = 7.31 bauds from the beginning, which is the previous byte. If you are 14% late, you'll be sampling at 8.5 + 14% = 9.69, which is the stop bit.
The maximum you can wonder away is 0.5 baud - this will keep you between 8.0 and 9.0. Thus you need 0.5/8.5 = 5.8% accuracy.
If you want to avoid frame errors, you need to sample stp bit correctly too - from 9.0 to 10.0 baud. Ths you need 0.5/9.5 = 5.2%.
Since both the receiver and transmitter may have errors, each of them is entitled only to half of the error. This guarantees the combined error to be satisfactory. Thus, the maximum error is 2.6% for each side.
Then there are transitions between bytes and jitter, which is not important at 9600 baud, but the faster you go, the more important it becomes. Say, if the rise/fall time is 50 ns, then at 5M baud, your target sampling interval for the stop byte is not from 1.8 to 2.0 us, but rather from 1.85 to 1.95 us. This doubles the clock accuracy requirement.